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Priv section 3.1.8 allows for but does not require that MTI be delegatable. So in that sense the answer is yes. But delegating MTI should generally be an unusual thing and some or many

By Greg Favor · #1216 ·

Question about mideleg

Dear architect， Can the M interrupt such as MTI be delegated to S mode ? Regards, Oscar Jupp

By Oscar Jupp · #1215 ·

Re: Svinval fence instructions traps from VU mode

Upon re-reading the relevant section in the hypervisor spec, I believe it is already specified that these should raise virtual-instruction exceptions when executed in VU-mode, hinging on the notion

By andrew@... · #1214 ·

Svinval fence instructions traps from VU mode

What should the behavior of the SFENCE.W.INVAL and SFENCE.INVAL.IR instructions be when executed in VU mode? The spec clearly spells out the behavior of the other S/H Fence/Inval instructions in VU

By John Ingalls · #1213 ·

AR (Architecture Review) Committee minutes for 11/29/22

We (the AR Committee) will be posting minutes of our (roughly) weekly meetings to discuss ISA issues that have been raised recently to the committee's attention, and to review RISC-V arch extensions

By Greg Favor · #1212 ·

Re: Quetion about xRET instruction

Dear architect, Thank you for your reply. I wonder how to emulate the hypervisor extension with trapping SRET on implementations that do not provide it. Regards, Oscar Jupp

By Oscar Jupp · #1211 ·

Re: Quetion about xRET instruction

I first read this as TSR meaning "Trap Service Routine", but now I understand that it is the mstatus.TSR bit.

By Allen Baum · #1210 ·

Re: Quetion about xRET instruction

The ability to execute SRET in M-mode provides M-mode the facility to trap, using TSR control, a SRET invoked in S-mode, and after handling the trap to redo the SRET. The SRET invoked in M-mode is not

By Ved Shanbhogue · #1209 ·

Quetion about xRET instruction

Dear architect, The spec section 3.3.2 said: “An xRET instruction can be executed in privilege mode x or higher, where executing a lower-privilege xRET instruction will pop the relevant

By Oscar Jupp · #1208 ·

Re: Question about supervisor interrupt in M mode

Dear Scott, Thank you very much! Regards, Oscar Jupp

By Oscar Jupp · #1207 ·

Re: Question about supervisor interrupt in M mode

Scott pointed out some issues about the way I framed the equations. I tried to make them symmetrical, to be more understandable, but Scott correctly points out there is some redundancy which is

By Allen Baum · #1206 ·

Re: Question about supervisor interrupt in M mode

From the privilege spec: "When a trap occurs in HS-mode or U-mode, it goes to M-mode, unless delegated by medeleg or mideleg, in which case it goes to HS-mode. When a trap occurs in VS-mode or

By Scott Johnson · #1205 ·

Re: Question about supervisor interrupt in M mode

Hi Scott, The spec does say this: Jeff

By Jeff Scott · #1204 ·

Re: Question about supervisor interrupt in M mode

For me, the most important non-obvious thing was realizing that mip+mie are the only two interrupt pending/enable registers. All the other *ip/*ie are [masked and/or shifted] views into mip/mie,

By Scott Johnson · #1203 ·

Re: Question about supervisor interrupt in M mode

Dear Scott, Thank you. I want to ask another question. When a hart is executing in U mode，doe the interrupt which trap to VS mode can be taken ？ ---Original--- From: "Scott

By Oscar Jupp · #1202 ·

Re: Question about supervisor interrupt in M mode

I agree this took me several readings of the spec to understand this. Pseudo-code would have saved myself and others a lot of time. Allen, thanks for taking the time to share this! Can we add

By Jeff Scott · #1201 ·

Re: Question about supervisor interrupt in M mode

I agree this part of the spec is hard to understand, and requires piecing together several diverse sources within the privileged spec. I don’t think your clarifications below are quite correct. More

By Scott Johnson · #1200 ·

Re: Question about supervisor interrupt in M mode

I think you’ve figured it out, but I’ve replied inline below anyway. Yes, exactly. Yes, that’s correct. It will show up in mip.STIP which is where M-mode interrupts are seen.

By Scott Johnson · #1199 ·

Re: Question about supervisor interrupt in M mode

Dear architect， I thought about it for a long time and finally figured it out. It's not weird, sip.STIP is read-only zero when the mideleg[5]==0. But hart is in S mode，but it have to take STI and

By Oscar Jupp · #1198 ·

Re: Question about supervisor interrupt in M mode

I'll stick my neck out again, and see if I get corrected again. This is the most difficult part of the spec for me to interpret. Priv spec sec 3.1.9 says(a) either the current privilege mode is M and

By Allen Baum · #1197 ·

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