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Re: Question about supervisor interrupt in M mode

Dear Scott， Thank you for your reply. Do you mean that : “Supervisor timer interrupt if mideleg[5]==0 is a interrupt for M mode. Supervisor timer interrupt if mideleg[5]==1 is a interrupt for S

By Oscar Jupp · #1196 ·

Re: Question about supervisor interrupt in M mode

Dear Jeff, How can I search on previous Summit proceedings for this pseudocode equation for “enabled”? Regards, Oscar Jupp

By Oscar Jupp · #1195 ·

Re: Question about supervisor interrupt in M mode

Yep, think of mti as first timer interrupt and sti as second timer interrupt. A pseudocode equation for “enabled” in the spec would make this easier. I think if you search on previous Summit

By Jeff Scott · #1194 ·

Re: Question about supervisor interrupt in M mode

No, that is not what it says or means. Interrupts for lower-privilege modes are always globally disabled regardless of xIE (i.e. the bit in mstatus for the current privilege mode e.g. mstatus.mie when

By Scott Johnson · #1193 ·

Re: Question about supervisor interrupt in M mode

Oscar, what you are missing is that STI, despite its name, is not for a lower-privilege mode when mideleg[5]==0. In that case the STI is destined for M-mode and therefore can be taken in any privilege

By Scott Johnson · #1192 ·

Re: Question about supervisor interrupt in M mode

Dear Allen, Thank you for your replay. How to understand next sentence: "Interrupts for higher-privilege modes, y>x, are always globally enabled regardless of the setting of the global yIE bit for

By Oscar Jupp · #1191 ·

Re: Question about supervisor interrupt in M mode

I think (and will be corrected if wrong) that the sentence should be interpreted as When xIE=0, Interrupts for lower-privilege modes, w<x are always globally disabled regardless of the setting of any

By Allen Baum · #1190 ·

Question about supervisor interrupt in M mode

Dear architect, Priv spec section 3.1.6.1 write: “When a hart is executing in privilege mode x, interrupts are globally enabled when xIE=1 and globally disabled when xIE=0. Interrupts for

By Oscar Jupp · #1189 ·

Re: Question about mip and vsip

Greg Favor wrote: To emphasize Greg's point, the next sentence says, "When V=1, an attempt to read or write a VS CSR directly by its own separate CSR address causes a virtual instruction

By John Hauser · #1188 ·

Re: Question about mip and vsip

Thanks for Allen and Greg! I learn a lot from you.

By Oscar Jupp · #1187 ·

Re: Question about mip and vsip

I believe I would agree with what Allen said. Regarding shadows, note that Priv section 2.1 says: CSRsthat are read-only at some lower privilege level are shadowed into separate CSR addresses if

By Greg Favor · #1186 ·

Re: Question about mip and vsip

Without a deep understanding of these particular bits (and Greg will correct me if I'm wrong) there are some general rules that should apply (I am unaware of any exceptions to this off the top of my

By Allen Baum · #1185 ·

Re: Question about mip and vsip

Per Priv section 2.2, 0x344 is read/write. And hip is also read-write. So the mip aliases of these hip bits are also read/write in mip. First, I think you mean section 5.1.3 in the latest draft of

By Greg Favor · #1184 ·

Re: Question about mip and vsip

Dear Greg, Thanks for your reply. 1. You said : “Priv section 9.4.3 defines these bits as aliases (of bits in hip), so yes - M-mode software can modify these bits.” But I don’t know they are

By Oscar Jupp · #1183 ·

Re: Question about mip and vsip

Priv section 9.4.3 defines these bits as aliases (of bits in hip), so yes - M-mode software can modify these bits. The vsip CSR - as with all vs* CSRs - is only accessible by HS-mode (and M-mode). As

By Greg Favor · #1182 ·

Question about mip and vsip

Dear architect, CSR mip and vsip are both WARL. But SPEC did not specify that : 1. Are the fields VSEIP，VSSIP，VSTIP in mip real-only ? Can M-mode software modify

By Oscar Jupp · #1181 ·

AR (Architecture Review) Committee minutes for 11/22/22

We (the AR Committee) will be posting minutes of our (roughly) weekly meetings to discuss ISA issues that have been raised recently to the committee's attention, and to review RISC-V arch extensions

By Greg Favor · #1180 ·

AR (Architecture Review) Committee minutes for 11/15

We (the AR Committee) will be posting minutes of our (roughly) weekly meetings to discuss ISA issues that have been raised recently to the committee's attention, and to review RISC-V arch extensions

By Greg Favor · #1179 ·

Re: Quetion about SSTC

See Priv section 9.6.1 for a description of the general rule for when to raise a virtual instruction versus illegal instruction exception. Greg

By Greg Favor · #1178 ·

Re: Quetion about SSTC

Dear architect, Thank you for your reply. Please clarify what kind of exceptions are generated by U and VU? I think when V=0, it is an illegal instruction exception, and when V=1 is a virtual

By Oscar Jupp · #1177 ·

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