We (the AR Committee) will be posting minutes of our (roughly) weekly meetings to discuss ISA issues that have been raised recently to the committee's attention, and to review RISC-V arch extensions

See Priv section 9.6.1 for a description of the general rule for when to raise a virtual instruction versus illegal instruction exception. Greg

Dear architect, Thank you for your reply. Please clarify what kind of exceptions are generated by U and VU? I think when V=0, it is an illegal instruction exception, and when V=1 is a virtual

Per Priv section 2.1 and Table 2.1, the CSR numbers encodes the lowest privilege level that can access the CSR. That level and all higher levels can access the CSR. So the first row of red should be

Dear architect, The stimecmp / vstimecmp” Extension said: "When STCE in menvcfg is zero, an attempt to access stimecmp or vstimecmp in a mode other than M-mode raises an

Dear Greg, Thank you for your reply. I am sorry that I miss the vital information. Regards, Oscar Jupp

The Sstc spec, in the Env Config Support section, says (with my underline): When STCE in menvcfg is zero, an attempt to access stimecmp or vstimecmp in a mode other than M-mode raises an illegal

See Priv section 1.1 and Unpriv section 1.2 for description. Greg

Dear architect, The privileged ISA said: “Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits for supervisorlevel timer interrupts. If implemented, STIP is read-only in

In the context of the overall Sstc spec, this text is correct in stating the baseline behavior when Sstc is implemented or not (and is precisely correct when Sstc is not implemented). And then the

The Sstc specification has this text (referring to whether STIP is writable): If the stimecmp register is not implemented, STIP is writable in mip, and may be written by M-mode software to deliver

Dear architect, I don't know the difference between illegal instruction exception and virtual instruction exception. For example: The CSR number of sstatus is 0x100,The CSR number of vsstatus is

Dear architect， Similarly, the hardwired bits prevent it from sending M interrupts to S mode. It is right? Regards, Oscar Jupp

Dear architect， Thanks! I learned a lot from you. I used to think that mip is used to indicate the summary of interrupts that need to be responded in M state, sip is used to indicate the summary of

No. Assuming bit 10 of hideleg is one, vsip.SEIP is an alias of hip.VSEIP. mip.VSEIP is an alias of hip.VSEIP. Bit 10 in mideleg is read-only one, so mip.VSEIP is visible as sip.VSEIP. Therefore both

They are all external interrupts to the physical machine. The hypervisor software will decide which, if any, of these external interrupts should be passed through to which guest OS, and direct the

Dear Paul Donahue, Thank you very much. I would like to ask another question. The VS level external interrupt has been delegated to the VS level (That is, mideleg[10] = 1 and hideleg[10] = 1). When an

Dear Scott Johnson, Thank you very much! You said: “If the hardware has GEILEN=0 then the external interrupt will first go to the hypervisor software, which can pass through the interrupt to the

The idea is that interrupts should be handled in the mode they target or a more privileged mode, not a less privileged mode. The hypervisor can optionally send VS interrupts to VS mode but the

External interrupts are passed through to the guest by setting `hip.VSEIP`, which the guest OS sees as `sip.SEIP`. The hypervisor software decides which interrupts should be passed through to which