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Per Priv section 2.1 and Table 2.1, the CSR numbers encodes the lowest privilege level that can access the CSR. That level and all higher levels can access the CSR. So the first row of red should be

By Greg Favor · #1176 ·

Quetion about SSTC

Dear architect, The stimecmp / vstimecmp” Extension said: "When STCE in menvcfg is zero, an attempt to access stimecmp or vstimecmp in a mode other than M-mode raises an

By Oscar Jupp · #1175 ·

Re: Meaning of Implemented in Sstc specification

Dear Greg, Thank you for your reply. I am sorry that I miss the vital information. Regards, Oscar Jupp

By Oscar Jupp · #1174 ·

Re: Meaning of Implemented in Sstc specification

The Sstc spec, in the Env Config Support section, says (with my underline): When STCE in menvcfg is zero, an attempt to access stimecmp or vstimecmp in a mode other than M-mode raises an illegal

By Greg Favor · #1173 ·

Re: Quetion about execution environment and platform-specific interrupt controller

See Priv section 1.1 and Unpriv section 1.2 for description. Greg

By Greg Favor · #1172 ·

Quetion about execution environment and platform-specific interrupt controller

Dear architect, The privileged ISA said: “Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits for supervisorlevel timer interrupts. If implemented, STIP is read-only in

By Oscar Jupp · #1170 ·

Re: Meaning of Implemented in Sstc specification

In the context of the overall Sstc spec, this text is correct in stating the baseline behavior when Sstc is implemented or not (and is precisely correct when Sstc is not implemented). And then the

By Greg Favor · #1169 ·

Meaning of Implemented in Sstc specification

The Sstc specification has this text (referring to whether STIP is writable): If the stimecmp register is not implemented, STIP is writable in mip, and may be written by M-mode software to deliver

By kenney@... · #1168 ·

Question about privilege

Dear architect, I don't know the difference between illegal instruction exception and virtual instruction exception. For example: The CSR number of sstatus is 0x100,The CSR number of vsstatus is

By Oscar Jupp · #1167 ·

Re: Question about CSR hedeleg and hideleg

Dear architect， Similarly, the hardwired bits prevent it from sending M interrupts to S mode. It is right? Regards, Oscar Jupp

By Oscar Jupp · #1166 ·

Re: Question about CSR hedeleg and hideleg

Dear architect， Thanks! I learned a lot from you. I used to think that mip is used to indicate the summary of interrupts that need to be responded in M state, sip is used to indicate the summary of

By Oscar Jupp · #1165 ·

Re: Question about CSR hedeleg and hideleg

No. Assuming bit 10 of hideleg is one, vsip.SEIP is an alias of hip.VSEIP. mip.VSEIP is an alias of hip.VSEIP. Bit 10 in mideleg is read-only one, so mip.VSEIP is visible as sip.VSEIP. Therefore both

By Scott Johnson · #1164 ·

Re: Question about guest external interrupt

They are all external interrupts to the physical machine. The hypervisor software will decide which, if any, of these external interrupts should be passed through to which guest OS, and direct the

By Scott Johnson · #1163 ·

Re: Question about CSR hedeleg and hideleg

Dear Paul Donahue, Thank you very much. I would like to ask another question. The VS level external interrupt has been delegated to the VS level (That is, mideleg[10] = 1 and hideleg[10] = 1). When an

By Oscar Jupp · #1162 ·

Re: Question about guest external interrupt

Dear Scott Johnson, Thank you very much! You said: “If the hardware has GEILEN=0 then the external interrupt will first go to the hypervisor software, which can pass through the interrupt to the

By Oscar Jupp · #1161 ·

Re: Question about CSR hedeleg and hideleg

The idea is that interrupts should be handled in the mode they target or a more privileged mode, not a less privileged mode. The hypervisor can optionally send VS interrupts to VS mode but the

By Paul Donahue · #1160 ·

Re: Question about guest external interrupt

External interrupts are passed through to the guest by setting `hip.VSEIP`, which the guest OS sees as `sip.SEIP`. The hypervisor software decides which interrupts should be passed through to which

By Scott Johnson · #1159 ·

Re: Question about CSR hedeleg and hideleg

Dear Paul Donahue, Thank you very much for your reply！ I have another question about hideleg。The privileged ISA said: “Among bits 15:0 of hideleg, bits 10, 6, and 2 (corresponding to the

By Oscar Jupp · #1158 ·

Re: Question about guest external interrupt

Dear Anup Patel, Thank you very much for your reply. I would like to continue to ask: If GEILEN is 0, CSR hgeip and hgeie will always be all zero. Then, hip.SGEIP is always 0. You said:

By Oscar Jupp · #1157 ·

Re: Question about guest external interrupt

If GEILEN is zero then there are no guest external interrupts but software (i.e. hypervisor) can still inject external interrupts using hvip CSR. In other words, software-injected external interrupts

By Anup Patel · #1156 ·

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