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Proposal for accelerating nested virtualization on RISC-V

Hi Jonathan, All cases for CSR accesses have not been thought through (initial draft) and written out. Regarding WARL CSR with hardwired bits, the HW will always read/write fixed values of hardwired b

By Anup Patel · #81 ·

Proposal for accelerating nested virtualization on RISC-V

A clarification is required in RISC-V H-Extension spec regarding scope of HSTATUS.VTVM bit. Currently as-per the spec, all virtual memory management instructions (both SFENCEs and HFENCEs) will trap t

By Anup Patel · #79 ·

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