RISC-V can already support KAISER now so I'm not sure why rv64 would need anything special for it? As a side note, that paper seriously understates the costs of KAISER. On other workloads it can be 2-

Presumably this should say "attempts to read or write the stimecmp register..."? Jonathan

I'd expect that S-mode software will also want to be able to receive RNMIs, so it is probably worth thinking through how that would work at the same time. Jonathan

Could you go into more detail on how nesting NMIs could work? Shouldn't it only be safe to execute MNRET with rnmie clear, because any NMI that came in between setting mnepc and executing MNRET would

Shouldn't exceptions during an NMI just jump to the normal exception handler? That seems like the simplest solution, and would be the behaviour if this extension didn't specify something different. Jo

One case where NMIs are used on x86 for non-fatal conditions is for performance monitoring. If an operating system wants to accurately measure its own performance, then ideally it should be able to sa

I suppose it depends on the exact design of the watchdog timer. In the scheme I'm familiar with, an NMI arrives every few seconds regardless of the state of the system. Then the interrupt handler is r

Your SATPU and SATPK registers seem to each contain: 64-bits of PPN, 32-bits of ASID, 4-bits for MODE and 28-bits reserved. But that adds up to 128-bits which is double the size of CSRs on 64-bit RISC

I don't think calling U-mode more privileged than VS-mode is quite right either. U-mode software cannot access VS-mode CSRs for instance. A different way of looking at it would be that VS-mode only ex

Oh, good point. I'd forgotten about the hstatus.HU bit which gives U-mode the ability to do loads and stores in the VS-mode address space. U-mode still doesn't have access to the VS-mode CSRs (or virt

What does "VS mode is enabled" mean? If you are referring to misa.H=1, then yes a core can be in U-mode while VS-mode is enabled. However, if by VS-mode enabled you mean V=1 (recalling that V stands f

How about sPMP is only used if satp.MODE=BARE or virtualization is enabled and hgatp.MODE=BARE? That would enable the trusted hypervisor case, while disallowing an S-mode operating system from enablin

It seems like we could just rename exception codes 12, 13, and 15 to "page fault / sPMP fault" and be done with it. Jonathan

It for instance rules out the case where M-mode uses PMP, HS-mode uses sPMP and paging, and VS-mode also uses sPMP and paging. That would be 5 stages of protection for every access! (Which is way wors

The proposed mstateenX CSRs feels very similar to misa. It almost seems like you could achieve the same thing as this proposal just by adding sisa and hisa (plus misa2, misa3, ...), but I think I've c

Why does all custom state need to be controlled with a single bit? Couldn't we just designate the upper 8 or 16 bits of each xstateenY register to be custom? Any software that wanted to disable all cu

What sort of device exposes regions of memory in I/O space? When I think of hypervisors emulating devices, all their registers typically do stuff when you write to them. Jonathan

"Old video cards and network cards" is a completely fair answer! If the PTE bit isn't needed otherwise, this seems like a reasonable use. Jonathan

I'd say that "must not" is too strong given that the behavior is still fully specified if that advice is ignored. This seems like the place for a non-normative note (if that) which basically just amou

In addition to the virtio NICs, QEMU can emulate an Intel e1000 NIC which stores packets in main memory and accesses them via DMA. I'd imagine that any other network cards of the same era would also d