I don't think calling U-mode more privileged than VS-mode is quite right either. U-mode software cannot access VS-mode CSRs for instance. A different way of looking at it would be that VS-mode only ex

Your SATPU and SATPK registers seem to each contain: 64-bits of PPN, 32-bits of ASID, 4-bits for MODE and 28-bits reserved. But that adds up to 128-bits which is double the size of CSRs on 64-bit RISC

I suppose it depends on the exact design of the watchdog timer. In the scheme I'm familiar with, an NMI arrives every few seconds regardless of the state of the system. Then the interrupt handler is r

One case where NMIs are used on x86 for non-fatal conditions is for performance monitoring. If an operating system wants to accurately measure its own performance, then ideally it should be able to sa

Shouldn't exceptions during an NMI just jump to the normal exception handler? That seems like the simplest solution, and would be the behaviour if this extension didn't specify something different. Jo

Could you go into more detail on how nesting NMIs could work? Shouldn't it only be safe to execute MNRET with rnmie clear, because any NMI that came in between setting mnepc and executing MNRET would

I'd expect that S-mode software will also want to be able to receive RNMIs, so it is probably worth thinking through how that would work at the same time. Jonathan

Presumably this should say "attempts to read or write the stimecmp register..."? Jonathan

RISC-V can already support KAISER now so I'm not sure why rv64 would need anything special for it? As a side note, that paper seriously understates the costs of KAISER. On other workloads it can be 2-

Could you clarify what suggestions you think we should implement? The KAISER paper describes a way of mitigating side channel attacks, but do you have specific lessons you think we should learn from i

In the worst case, a software page table walk isn't that expensive.

Errr... disregard that second part, I misread the previous email

Perhaps “all state no longer associated with any active extension is UNSPECIFIED”? But it also might be slightly cleaner to talk about the state being unspecified right after an extension is reactivat

You can achieve the same thing using the hypervisor extension analogously to how M/U systems can avoid user-level interrupts by switching to M/S/U. Instead of running the kernel in S-mode and drivers

I'd also strongly argue for there only being a single configuration for both virtualized and non-virtualized systems. The fewer different cases that software has to handle, the better for everyone. Th

It depends on how you are using them. For x86-64, Linux actually only uses 4 ASID bits (out of the 12 available) because it assigns them per-core and recycles them aggressively. However, if you instea

My understanding is that sfence.vma's are never required by the RISC-V spec, only that failing to do them can cause undesirable but well defined behavior. I'd suggest that the same be true here. We co

Couldn't you just change the wording to be "disabled" when referring to having misa.H=0 and leave "unimplemented" to mean having misa.H hardwired to 0? Jonathan

If hstatus.SPV=0, then SRET behaves like normal. And since that bit will stay zero unless some code messes with hypervisor CSRs, it should be sufficient to just have the reset state initialize it that

Why would that be a problem? As long as you don't issue any HS-mode instructions or touch any of the hypervisor CSRs then any code should run the same. Jonathan