We would like to restate that this is a peer review, not public. Thanks, George, Ved

Dear all, With the following mail we would like to ask for a 2 week public review on the proposed Shadow Stack and Landing Pads (SSLP) specification. You can find the specification document on GitHub

It is indeed valid for the page-table walker not to observe stores that have occurred since the last SFENCE.VMA instruction. That thread is 4.5 years old, and the RISC-V Linux kernel port has changed

Hi All, Suppose a hart executes a store to create a new PTE, and then that hart executes a SINVAL.VMA with rs1 and rs2 set so as to affect the address of that PTE. Are subsequent page walks guaranteed

Hi Nick, yes on both - we will plan to end by mid-afternoon on Thursday. Also keeping a zoom call on the 2nd and 3rd day morning (pacific) sounds like a good idea to summarize the previous day and con

Thanks Ravi, I think morning (Pacific time) zoom update calls (one hour?) on the Wednesday and Thursday is probably more social for most people? Than the proposed end of day call (Pacific time). Can w

Started discussion and review of the Sscdeleg and Zicntrpmf fast track extensions, including discussion about how their CSRs are to be used and accessed software. Prior ARC minutes (from two meetings

Started discussion and review of the Sscdeleg and Zicntrpmf fast track extensions, including discussion about how their CSRs are to be used and accessed software. Prior ARC minutes (from two meetings

Hi, Following up from the discussion at the Security HC this week - we discussed the pros of conducting a f2f for the mem isolation topic and there was general consensus to go ahead with it. The days

We discussed a proposal for compressed variants of a subset of the CFI instructions and recommend pursuing it. (This proposal hasn't been written down yet; we will do so soon and will promptly circula

Given that we are all architects, how about we first agree on the problem we are trying solve before debating potential solutions? Ravi, what problem(s) are you trying to solve? I'm guessing its somet

Hello Ravi, It won't be easy for many of us to come to such an event that's focused solely on security and is not a public RISC-V event, or let's say an event large enough that our companies/organizat

Hi Priv TG, In various TGs under the Security HC, and in discussions with folks from this Priv TG, we have been discussing the concept of a dynamic PMA for physical memory isolation (page granular). T

Thanks Ravi, Is this on the agenda for the TC SIG or Security HC this week? Agree it makes sense with focussed meetings on these topics – isolation model, device management model, interoperability wit

Greetings, As active participants in the Security HC know, recently we have been discussing the security model for RISC-V with a focus on (domain) isolation framework. A lot of us have been meeting in

Overview Most of the 2023-02-28 Architecture Review Committee (ARC) discussion concerned the Pointer Masking proposal. This was followed by a brief update on Zimops for CFI, and generalizing the AIA i

Thank you all for your response! That make much sense to me and what I am about to do. Best regards, Oscar Allen Baum <allen.baum@...> 于2023年3月4日周六 02:23写道：

Colleagues, James Stine, Ross Thompson, Sarah Harris, and I are writing a textbook on RISC-V System-on-Chip Design, to be published by Elsevier in 2024. It is written around an open-source configurabl

Ah,yes, as John just posted, by this as well Shtvala htval must be written with the faulting guest physical address in all circumstances permitted by the ISA. On Fri, Mar 3, 2023 at 10:21 AM Allen Bau

Basically, the option to load xtval or mtval2 (or not) on any specific exception is a (currently) unnamed architectural option. There is no way (currently) to discover this without either - trying to