I only skimmed some of the proposal, but one thing I noticed is that there doesn't seem to be much limit over who can set the current RCID and MCID. In particular, with the H-extension it looks like a

I think the fact that the current platform spec draft lacks any way for S-mode to toggle misa.H, for S-mode to request a specific value, or even a way for configuring M-mode to set/unset misa.H at boo

As I understand it, this is intentional. Access faults are likely to be substantially less frequent than page faults so the performance overhead of forwarding them from HS-mode to VS-mode shouldn't be

Couldn't the reset state itself just have a5=<pointer>? I don't see why that would be substantially harder to implement than a reset state with CSR[0x750]=<pointer>. Jonathan

I'm not sure I follow. I understand that the low-level and high-level discovery mechanisms are different, but is there a reason that the pointer to the low-level discovery method needs to be passed vi

Why does it need to be a CSR? In other parts of the boot flow the device tree pointer is passed via a normal general purpose register. Why can't the same be done here? Jonathan

Is RISC-V already facing a shortage of CSRs?

Wouldn't you also want to isolate different interrupt handlers from each other and from any non-interrupt handler user code running on the system? With the N-extension itself none of that would be pos

Agreed with Andrew that the N-extension isn't useful for M/U systems because it is equivalent to adding S-mode with satp hardwired to zero. The N-extension adds 8 CSRs while S-mode has a total of 12 C

In addition to the virtio NICs, QEMU can emulate an Intel e1000 NIC which stores packets in main memory and accesses them via DMA. I'd imagine that any other network cards of the same era would also d

I'd say that "must not" is too strong given that the behavior is still fully specified if that advice is ignored. This seems like the place for a non-normative note (if that) which basically just amou

"Old video cards and network cards" is a completely fair answer! If the PTE bit isn't needed otherwise, this seems like a reasonable use. Jonathan

What sort of device exposes regions of memory in I/O space? When I think of hypervisors emulating devices, all their registers typically do stuff when you write to them. Jonathan

Why does all custom state need to be controlled with a single bit? Couldn't we just designate the upper 8 or 16 bits of each xstateenY register to be custom? Any software that wanted to disable all cu

The proposed mstateenX CSRs feels very similar to misa. It almost seems like you could achieve the same thing as this proposal just by adding sisa and hisa (plus misa2, misa3, ...), but I think I've c

It for instance rules out the case where M-mode uses PMP, HS-mode uses sPMP and paging, and VS-mode also uses sPMP and paging. That would be 5 stages of protection for every access! (Which is way wors

It seems like we could just rename exception codes 12, 13, and 15 to "page fault / sPMP fault" and be done with it. Jonathan

How about sPMP is only used if satp.MODE=BARE or virtualization is enabled and hgatp.MODE=BARE? That would enable the trusted hypervisor case, while disallowing an S-mode operating system from enablin

What does "VS mode is enabled" mean? If you are referring to misa.H=1, then yes a core can be in U-mode while VS-mode is enabled. However, if by VS-mode enabled you mean V=1 (recalling that V stands f

Oh, good point. I'd forgotten about the hstatus.HU bit which gives U-mode the ability to do loads and stores in the VS-mode address space. U-mode still doesn't have access to the VS-mode CSRs (or virt