This is a call for chair and vice-chair candidates for the recently created Performance Analysis SIG (umbrella: Privileged Software HC) All candidates must submit a biography (bio) and statements of i

Oops, I guess the web interface doesn't include the text from the message I was responding to. Here it is, from Krste: | I would like a clarification on whether this replaces the existing NMI, or are

Reviving this old thread. What is the status of this proposal? I'd like to explore using RNMIs for performance counter overflow interrupts, in order to support profiling while interrupts are masked.

Hi all, I'd like to start a discussion on adding an ability to delegate hardware performance monitoring counters to S/HS mode, and further to VS mode. In “Rich OS” server environments, PMU resources a

Fair enough. But it would be nice to have the full definition of instret in one place. To discern that instructions that cause exceptions don't increment the counter requires reading the ECALL/EBREAK

Thanks guys. It would be good to clarify this in the spec, so there is no confusion. x86's INST_RETIRED.ALL, for instance, does increment for interrupts and exceptions.

You just beat me, I had a mail to the same effect in progress. For instructions I agree that events, like instret, should be based on the originating PL. Other uarch events, like cycles or stalls, wil

Hi there, I'm working on PMU definition at Rivos, and had some questions about the HPM architecture (including Sscofpmf extension). I started just a couple of weeks ago, and while I tried to do my hom