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Call for Chair/Vice-Chair Candidates for Performance Analysis SIG
This is a call for chair and vice-chair candidates for the recently created Performance Analysis SIG (umbrella: Privileged Software HC) All candidates must submit a biography (bio) and statements of i
This is a call for chair and vice-chair candidates for the recently created Performance Analysis SIG (umbrella: Privileged Software HC) All candidates must submit a biography (bio) and statements of i
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By
Beeman Strong
· #1032
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Resumable NMI proposal
Oops, I guess the web interface doesn't include the text from the message I was responding to. Here it is, from Krste: | I would like a clarification on whether this replaces the existing NMI, or are
Oops, I guess the web interface doesn't include the text from the message I was responding to. Here it is, from Krste: | I would like a clarification on whether this replaces the existing NMI, or are
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By
Beeman Strong
· #1031
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Resumable NMI proposal
Reviving this old thread. What is the status of this proposal? I'd like to explore using RNMIs for performance counter overflow interrupts, in order to support profiling while interrupts are masked.
Reviving this old thread. What is the status of this proposal? I'd like to explore using RNMIs for performance counter overflow interrupts, in order to support profiling while interrupts are masked.
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By
Beeman Strong
· #1030
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Delegating counters
Hi all, I'd like to start a discussion on adding an ability to delegate hardware performance monitoring counters to S/HS mode, and further to VS mode. In “Rich OS” server environments, PMU resources a
Hi all, I'd like to start a discussion on adding an ability to delegate hardware performance monitoring counters to S/HS mode, and further to VS mode. In “Rich OS” server environments, PMU resources a
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By
Beeman Strong
· #960
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Questions on HPMs
Fair enough. But it would be nice to have the full definition of instret in one place. To discern that instructions that cause exceptions don't increment the counter requires reading the ECALL/EBREAK
Fair enough. But it would be nice to have the full definition of instret in one place. To discern that instructions that cause exceptions don't increment the counter requires reading the ECALL/EBREAK
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By
Beeman Strong
· #921
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Questions on HPMs
Thanks guys. It would be good to clarify this in the spec, so there is no confusion. x86's INST_RETIRED.ALL, for instance, does increment for interrupts and exceptions.
Thanks guys. It would be good to clarify this in the spec, so there is no confusion. x86's INST_RETIRED.ALL, for instance, does increment for interrupts and exceptions.
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By
Beeman Strong
· #918
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Questions on HPMs
You just beat me, I had a mail to the same effect in progress. For instructions I agree that events, like instret, should be based on the originating PL. Other uarch events, like cycles or stalls, wil
You just beat me, I had a mail to the same effect in progress. For instructions I agree that events, like instret, should be based on the originating PL. Other uarch events, like cycles or stalls, wil
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By
Beeman Strong
· #917
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Questions on HPMs
Hi there, I'm working on PMU definition at Rivos, and had some questions about the HPM architecture (including Sscofpmf extension). I started just a couple of weeks ago, and while I tried to do my hom
Hi there, I'm working on PMU definition at Rivos, and had some questions about the HPM architecture (including Sscofpmf extension). I started just a couple of weeks ago, and while I tried to do my hom
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By
Beeman Strong
· #907
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