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RISC-V H-Extension Nested MMU Test-suite
Hi All,
We now have a simple Nested MMU (i.e. Two-stage MMU) test-suite available as part of Xvisor white-box testing framework. This test-suite runs in HS-mode and does nested MMU testing using the HSV/HLV instructions. This means Nested MMU (i.e. Two-stage MMU) testing is achieved without creating any Guest/VM on Xvisor. To run the Xvisor nested MMU test-suite we only need OpenSBI firmware and Xvisor binary. Currently, Xvisor nested MMU test-suite works on both QEMU and Spike. Refer following READMEs to try Xvisor nested MMU test-suite: https://github.com/avpatel/xvisor-next/blob/master/docs/riscv/riscv64-nested-mmu-test-qemu.txt https://github.com/avpatel/xvisor-next/blob/master/docs/riscv/riscv64-nested-mmu-test-spike.txt https://github.com/avpatel/xvisor-next/blob/master/docs/riscv/riscv32-nested-mmu-test-qemu.txt In future, the Xvisor Nested MMU test-suite will also help in implementing nested hypervisors. Regards, Anup |
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