Proposal: Accelerating Handling User-level Interrupts


Yifei Jiang
 

Hi all,

 

When we applied user-level interrupts in N extension to the Unix-like OS, there is no way to directly handle user-level interrupts in userspace bypassing the kernel. This makes little use of the user-level interrupt mechanism. In this proposal, we provide a hardware-assisted context switch mechanism to accelerate handling interrupts in the U-mode of Unix-like OS. Our proposal is implemented on the QEMU simulator and KVM virtualization architecture. Evaluation results show that our proposal improves the block performance by 2.63% to 7.56%. Also, more benefits can be gained by combining this proposal with some other optimizations.

 

The attachment is the detailed proposal. Any comments are welcome.

 

Regards,

Yifei


mark
 

i remember using DEC VAX ancillary control processes and writing knob and trackball device drivers in user land in the early 80s. I tried to find something describing this but I think it is lost to antiquity.

does anyone know how they did it? i don't remember ever losing an interrupt or affecting the rest of the system  but then again everything is relative.

mark

On Fri, Sep 18, 2020 at 1:07 AM Yifei Jiang via lists.riscv.org <jiangyifei=huawei.com@...> wrote:
















Hi all,



 



When we applied user-level interrupts in N extension to the Unix-like OS, there is no way to directly handle user-level interrupts in userspace bypassing the kernel. This makes little use of the user-level interrupt mechanism.

In this proposal, we provide a hardware-assisted context switch mechanism to accelerate handling interrupts in the U-mode of Unix-like OS. Our proposal is implemented on the QEMU simulator and KVM virtualization architecture. Evaluation results show that our

proposal improves the block performance by 2.63% to 7.56%. Also, more benefits can be gained by combining this proposal with some other optimizations.



 



The attachment is the detailed proposal. Any comments are welcome.



 



Regards,



Yifei

















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Mark I Himelstein
CTO RISC-V International
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twitter @mark_riscv