Clarification on writing MXL field of the MISA CSR
I believe what you're missing is the caveat in the first sentence of 2.4: "the values of the writable fields and bits of the new-width CSR are, unless specifiedtoggle quoted message Show quoted text
otherwise, determined from the previous-width CSR as though by this algorithm".
For misa, the MXL field is specified as being in bit positions (MXLEN-1) and (MXLEN-2). I'd say that counts as "specified otherwise".
On Wed, Mar 10, 2021 at 03:07 PM, Joseph Rahmeh wrote:
Joseph Rahmeh <joseph.rahmeh@...>
On a 64-bit implementation RISCV that supports a writable XML field in the MISA CSR and that supports writing 1 to that field (to turn on 32-bit mode), if we apply section 2.4 (CSR width modulation) to the MISA CSR then the XML field would end up with a 0 no matter what we attempt to write to it. This does not seem right.
Say we are in 32-bit mode and XML has the value 1. If we write 1 to XML, this will change MXLEN to 64. Following section 2.4 we get the following:
Top 32 bits of the temporary register are set to zero since new width is larger than old width.
Writable field XML in its new position (bits 62 and 63) is copied from corresponding location in temporary register: New XML gets 0.
Say we are in 64-bit mode and XML has the value 2. If we write 1 to XML, this will change MXLEN to 32. Following section 2,4 we get the following:
Bits 31 and 30 are read only in the previous width MISA. Consequently bits 31 and 30 will be zero in the temporary register. When writable fields in the new width MISA are copied from the temporary register, the new XML fields gets 0.
Is it implied that software should write the XML field twice in order to put in it a value consistent with MXLEN? Once in its previous width MISA and again after MXLEN changes?
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