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Question about mip and vsip

John Hauser
 

Greg Favor wrote:
The vsip CSR - as with all vs* CSRs - is only accessible by HS-mode (and
M-mode). As the vsip definition says, "When V=1, vsip and vsie substitute
for the usual sip and sie, so instructions that normally read or modify
sip/sie actually access vsip/vsie instead."
To emphasize Greg's point, the next sentence says, "When V=1, an
attempt to read or write a VS CSR directly by its own separate CSR
address causes a virtual instruction exception."

Oscar Jupp asked:
2.  Are the fields SEIP，SSIP，STIP in vsip real-only ? Can VS-mode
software modify these bit fields?
By the text quoted above, attempting to access vsip directly from VS
mode raises a virtual instruction exception. (V = 1 in VS mode.)

What about accessing sip from VS mode, which is really vsip? Because
the whole purpose of VS mode is to be a virtual S mode, the general
default assumption should be that VS mode provides an equivalent
execution environment as S mode. Therefore, what VS mode sees of
sip is what the Privileged Architecture says is true of sip in the
Supervisor-Level chapter (Section 4.1.3, "Supervisor Interrupt
Registers (sip and sie)"): "If implemented, SEIP is read-only
in sip...." "If implemented, STIP is read-only in sip...." "If
implemented, SSIP is writable in sip...."

- John Hauser
Oscar Jupp
 

Thanks for Allen and Greg!
I learn a lot from you. 

---- Replied Message ----
From Allen Baum<allen.baum@...>
Date 11/27/2022 15:07
To Greg Favor<gfavor@...>
Cc jupposcar<jupposcar@...> ,
 tech-privileged@...<tech-privileged@...>
Subject Re: [RISC-V] [tech-privileged] Question about mip and vsip
Without a deep understanding of these particular bits (and Greg will correct me if I'm wrong) there are some general rules that should apply
(I am unaware of any exceptions to this off the top of my head, but if they are anywhere, they'd probably be in the interrupt and hypervisor CSRs): 
 A bit that is RW accessible to a lower privilege mode should always be RW at a higher privilege mode (though it may be accessed at a different address because of the way hypervisor extension works)
  If the CSR is accessible to the accessing mode at all, and is not in the ReadOnly CSR ranges, then
  if a bit is described as an alias,      then it should be read/write if they are read/write at the higher privilege level
  if a bit is described as an shadow, then it should be read-only  even if they are read/write at the higher privilege level
  A CSR which is described as a "restricted view" would have some bits that aliased at a higher privilege level, and be read-only zero at lower privilege levels.


On Sat, Nov 26, 2022 at 10:56 PM Greg Favor <gfavor@...> wrote:
On Sat, Nov 26, 2022 at 8:41 PM jupposcar <jupposcar@...> wrote:
1. You said : “Priv section 9.4.3 defines these bits as aliases (of bits in hip), so yes - M-mode software can modify these bits.” 
But I don’t know they are read-only aliases ? or read-write aliases ? In other word, Can the CSR instruction  with the CSR number 0x344 (mip) modify these bits?

Per Priv section 2.2, 0x344 is read/write.  And hip is also read-write.  So the mip aliases of these hip bits are also read/write in mip.
 
Or only CSR instruction with the CSR number 0x644 (hip) can modify these bits?

2. The ISA said : “If implemented, SEIP is read-only in sip."(Priv section 4.3.1)
It means sip.SEIP is read-only for S-mode. Similarly, is vsip.SEIP read-only for VS-mode ?

First, I think you mean section 5.1.3 in the latest draft of the Priv spec.  And yes, you're correct.
 
Greg
Greg Favor
 

I believe I would agree with what Allen said.  Regarding shadows, note that Priv section 2.1 says:

CSRs that are read-only at some lower privilege level are shadowed into separate CSR addresses if they are made read-write at a higher privilege level. This avoids trapping permitted lower-privilege accesses while still causing traps on illegal accesses. Currently, the counters are the only shadowed CSRs.  

Greg

On Sat, Nov 26, 2022 at 11:07 PM Allen Baum <allen.baum@...> wrote:
Without a deep understanding of these particular bits (and Greg will correct me if I'm wrong) there are some general rules that should apply
(I am unaware of any exceptions to this off the top of my head, but if they are anywhere, they'd probably be in the interrupt and hypervisor CSRs): 
 A bit that is RW accessible to a lower privilege mode should always be RW at a higher privilege mode (though it may be accessed at a different address because of the way hypervisor extension works)
  If the CSR is accessible to the accessing mode at all, and is not in the ReadOnly CSR ranges, then
  if a bit is described as an alias,      then it should be read/write if they are read/write at the higher privilege level
  if a bit is described as an shadow, then it should be read-only  even if they are read/write at the higher privilege level
  A CSR which is described as a "restricted view" would have some bits that aliased at a higher privilege level, and be read-only zero at lower privilege levels.


On Sat, Nov 26, 2022 at 10:56 PM Greg Favor <gfavor@...> wrote:
On Sat, Nov 26, 2022 at 8:41 PM jupposcar <jupposcar@...> wrote:
1. You said : “Priv section 9.4.3 defines these bits as aliases (of bits in hip), so yes - M-mode software can modify these bits.” 
But I don’t know they are read-only aliases ? or read-write aliases ? In other word, Can the CSR instruction  with the CSR number 0x344 (mip) modify these bits?

Per Priv section 2.2, 0x344 is read/write.  And hip is also read-write.  So the mip aliases of these hip bits are also read/write in mip.
 
Or only CSR instruction with the CSR number 0x644 (hip) can modify these bits?

2. The ISA said : “If implemented, SEIP is read-only in sip."(Priv section 4.3.1)
It means sip.SEIP is read-only for S-mode. Similarly, is vsip.SEIP read-only for VS-mode ?

First, I think you mean section 5.1.3 in the latest draft of the Priv spec.  And yes, you're correct.
 
Greg
Allen Baum
 

Without a deep understanding of these particular bits (and Greg will correct me if I'm wrong) there are some general rules that should apply
(I am unaware of any exceptions to this off the top of my head, but if they are anywhere, they'd probably be in the interrupt and hypervisor CSRs): 
 A bit that is RW accessible to a lower privilege mode should always be RW at a higher privilege mode (though it may be accessed at a different address because of the way hypervisor extension works)
  If the CSR is accessible to the accessing mode at all, and is not in the ReadOnly CSR ranges, then
  if a bit is described as an alias,      then it should be read/write if they are read/write at the higher privilege level
  if a bit is described as an shadow, then it should be read-only  even if they are read/write at the higher privilege level
  A CSR which is described as a "restricted view" would have some bits that aliased at a higher privilege level, and be read-only zero at lower privilege levels.


On Sat, Nov 26, 2022 at 10:56 PM Greg Favor <gfavor@...> wrote:
On Sat, Nov 26, 2022 at 8:41 PM jupposcar <jupposcar@...> wrote:
1. You said : “Priv section 9.4.3 defines these bits as aliases (of bits in hip), so yes - M-mode software can modify these bits.” 
But I don’t know they are read-only aliases ? or read-write aliases ? In other word, Can the CSR instruction  with the CSR number 0x344 (mip) modify these bits?

Per Priv section 2.2, 0x344 is read/write.  And hip is also read-write.  So the mip aliases of these hip bits are also read/write in mip.
 
Or only CSR instruction with the CSR number 0x644 (hip) can modify these bits?

2. The ISA said : “If implemented, SEIP is read-only in sip."(Priv section 4.3.1)
It means sip.SEIP is read-only for S-mode. Similarly, is vsip.SEIP read-only for VS-mode ?

First, I think you mean section 5.1.3 in the latest draft of the Priv spec.  And yes, you're correct.
 
Greg
Greg Favor
 

On Sat, Nov 26, 2022 at 8:41 PM jupposcar <jupposcar@...> wrote:
1. You said : “Priv section 9.4.3 defines these bits as aliases (of bits in hip), so yes - M-mode software can modify these bits.” 
But I don’t know they are read-only aliases ? or read-write aliases ? In other word, Can the CSR instruction  with the CSR number 0x344 (mip) modify these bits?

Per Priv section 2.2, 0x344 is read/write.  And hip is also read-write.  So the mip aliases of these hip bits are also read/write in mip.
 
Or only CSR instruction with the CSR number 0x644 (hip) can modify these bits?

2. The ISA said : “If implemented, SEIP is read-only in sip."(Priv section 4.3.1)
It means sip.SEIP is read-only for S-mode. Similarly, is vsip.SEIP read-only for VS-mode ?

First, I think you mean section 5.1.3 in the latest draft of the Priv spec.  And yes, you're correct.
 
Greg
Oscar Jupp
 

Dear Greg,
Thanks for your reply.
1. You said : “Priv section 9.4.3 defines these bits as aliases (of bits in hip), so yes - M-mode software can modify these bits.” 
But I don’t know they are read-only aliases ? or read-write aliases ? In other word, Can the CSR instruction  with the CSR number 0x344 (mip) modify these bits? Or only CSR instruction with the CSR number 0x644 (hip) can modify these bits?

2. The ISA said : “If implemented, SEIP is read-only in sip."(Priv section 4.3.1)
It means sip.SEIP is read-only for S-mode. Similarly, is vsip.SEIP read-only for VS-mode ?


---- Replied Message ----
From Greg Favor<gfavor@...>
Date 11/27/2022 06:16
To Oscar Jupp<jupposcar@...>
Cc tech-privileged@...<tech-privileged@...>
Subject Re: [RISC-V] [tech-privileged] Question about mip and vsip
On Sat, Nov 26, 2022 at 4:38 AM Oscar Jupp <jupposcar@...> wrote:
Dear architect,
CSR mip and vsip are both WARL. But SPEC did not specify that :
1.  Are the fields VSEIP，VSSIP，VSTIP in mip real-only ? Can M-mode software modify these bit fields?

Priv section 9.4.3 defines these bits as aliases (of bits in hip), so yes - M-mode software can modify these bits.

2.  Are the fields SEIP，SSIP，STIP in vsip real-only ? Can VS-mode software modify these bit fields?

The vsip CSR - as with all vs* CSRs - is only accessible by HS-mode (and M-mode).  As the vsip definition says, "When V=1, vsip and vsie substitute for the usual sip and sie, so instructions that normally read or modify sip/sie actually access vsip/vsie instead."

In other words, VS-mode software (just like S/HS-mode software) has read/write access to sip, but in the case of VS-mode software (i.e. V=1) it actually accesses vsip and not sip.

Greg
Greg Favor
 

On Sat, Nov 26, 2022 at 4:38 AM Oscar Jupp <jupposcar@...> wrote:
Dear architect,
CSR mip and vsip are both WARL. But SPEC did not specify that :
1.  Are the fields VSEIP，VSSIP，VSTIP in mip real-only ? Can M-mode software modify these bit fields?

Priv section 9.4.3 defines these bits as aliases (of bits in hip), so yes - M-mode software can modify these bits.

2.  Are the fields SEIP，SSIP，STIP in vsip real-only ? Can VS-mode software modify these bit fields?

The vsip CSR - as with all vs* CSRs - is only accessible by HS-mode (and M-mode).  As the vsip definition says, "When V=1, vsip and vsie substitute for the usual sip and sie, so instructions that normally read or modify sip/sie actually access vsip/vsie instead."

In other words, VS-mode software (just like S/HS-mode software) has read/write access to sip, but in the case of VS-mode software (i.e. V=1) it actually accesses vsip and not sip.

Greg
Oscar Jupp
 

Dear architect,
CSR mip and vsip are both WARL. But SPEC did not specify that :
1.  Are the fields VSEIP，VSSIP，VSTIP in mip real-only ? Can M-mode software modify these bit fields?
2.  Are the fields SEIP，SSIP，STIP in vsip real-only ? Can VS-mode software modify these bit fields?

Regards,
Oscar Jupp

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