Question about The RISC-V Advanced Interrupt Architecture

John Hauser

Oscar Jupp wrote:
To whom it may concern,
This is table 7.1 of the RISC-V Advanced Interrupt Architecture spec (Document Version 1.0-RC1).

Why vsip[n] and vsie[n] is alias of sip[n] and sie[n], when hideleg[n] = 1?

The Privileged spec write:
“When bit 10 of hideleg is zero, vsip.SEIP and vsie.SEIE are read-only zeros. Else, vsip.SEIP
and vsie.SEIE are aliases of hip.VSEIP and hie.VSEIE.
When bit 6 of hideleg is zero, vsip.STIP and vsie.STIE are read-only zeros. Else, vsip.STIP
and vsie.STIE are aliases of hip.VSTIP and hie.VSTIE.
When bit 2 of hideleg is zero, vsip.SSIP and vsie.SSIE are read-only zeros. Else, vsip.SSIP and
vsie.SSIE are aliases of hip.VSSIP and hie.VSSIE."
The caption on Table 7.1 says:

The effects of hideleg and hvien on vsip and vsie for major
interrupts 13-63.

Bits 10, 6, and 2 in vsip are major interrupts 10, 6, and 2 for
VS level, so all of them are outside the range covered by the table
(major interrupts 16-63).

- John Hauser