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Address Mapping Questions
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Dear team,
This may be a basic question: I am trying to figure out where in the physical memory map are the "mtime" and "mtimecmp" registers to be placed. Per the privileged spec, these registers are memory-mapped, but I could not find an address specification for these registers. Did I somehow miss finding this piece of information from the spec or is it actually not specified? If the latter, is there a different place where it is specified that an implementation should comply with? Another question: are CSRs also memory mapped? In debug mode? Thank you and apologies if these questions have been discussed and resolved before. Best Regards Nagendra |
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andrew@...
The memory map isn't in the spec because it's platform-defined. Some folks use the SiFive CLINT as a de facto standard for the address map for mtime[cmp] and MSIP registers. QEMU supports this as well. You can find the CLINT memory map in Chapter 8 of https://sifive.cdn.prismic.io/sifive/86e05812-e9cd-4553-bfef-c7e715088055_sifive_coreip_U54MC_AXI4_rtl_v19_08p2p0_release_manual.pdf On Thu, Jun 4, 2020 at 5:34 PM Nagendra Gulur <nagendra.gd@...> wrote: Dear team, |
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Thanks Andrew - yes this de facto is great information. Is there any platform-level effort to convert this to a standard? Best Regards Nagendra On Thu, Jun 4, 2020 at 8:01 PM Andrew Waterman <andrew@...> wrote:
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andrew@...
It's something that could conceivably be standardized by the Unix platform task group, but I'm unaware as to whether that's in their plan of record. On Thu, Jun 4, 2020 at 6:46 PM Nagendra Gd <nagendra.gd@...> wrote:
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In re. your other question: > Another question: are CSRs also memory mapped? In debug mode? No, CSRs are not specified as memory-mapped (an implementation may choose to do so), even in Debug Mode. The Debug Module (not the CPU) has an 'Access Register' abstract command (see Sec. 3.6.1 "Access Register" section of the Debug Module Spec) where it uses an Abstract Register Number to name all GPRs, FPRs and CSRs (see Table 3.3 in the Debug Spec). 0x0000-0x0FFF are used for CSRs, 0x1000-0x101F for GPRs, and 0x1020-103F for FPRs. This is not a 'memory-mapping' of CSRs, just the internal Debug Module (and GDB's) convention on how to name all registers. Best regards, Nikhil |
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A bit more on that. There are a few debug CSRs which can be accessed as both CSRs and as Debug registers, specifically for communication. Otherwise, debug registers are in their own address space, and accessible only through the debug module. As Nikhil says, there is also a command to enable access to all CSRs through the debug module by writing specific debug command register (Abstract Command) which will cause the value of a CSR to be read from/written to a communication debug register (Data0 and possibly Data1) . On Fri, Jun 5, 2020 at 5:15 AM Nikhil Rishiyur <nikhil@...> wrote:
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