My apologies if this topic was discussed and archived. I did search but mostly came across Unix platform style discussions on interrupt support. But my interest here is mostly around RTOS-based low-end, low-power 32-bit MCUs built with RV32I/RV32E class cores.

In these MCUs, fast save/restore before/after interrupts is essential for both real-time performance and power. I am looking at some guidance in this regard as to what the architecture specification outlines. From reading the unprivileged and privileged specs, I inferred that the hardware would need to save all caller-saved registers to the stack before invoking the interrupt service routine  (plus mcause etc). Is this correct? This is not spelt out as a requirement of the EE or the hardware but it does show up in various search results that this act of saving caller-saved registers is C-ABI compatible. At the same time, I came across the fast interrupt spec on github that describes the CLIC and also mentions C-ABI.

So .. I guess the questions are:

1. What is a minimum set of state to be saved to be RISC-V compliant?
2. If caller-saved registers are not saved, then we will not be C-ABI compatible. Does this potentially create a SW ecosystem fragmentation where some RV32 vendors support C-ABI compatible interrupts and others do not?  
3. Is the CLIC spec on github intended to become a part of the body of RISC-V specifications?

Thanks
Nagendra