1. Topics
  2. Is behavior for out-of-range physical addresses explicitly specified?

Is behavior for out-of-range physical addresses explicitly specified?

kenney@...
 

Does the RISC-V architecture require particular behavior when physical addresses outside the implemented range are used?

Suppose for example that 56 bits of physical memory are implemented. Is an access with non-zero bits in the range [63:56] required to trap, or is it permitted to discard these bits prior to any PMP checks, effectively wrapping the address range?

(I'm thinking about a system with M+U modes only here.)

Thanks,

James.
Abel Bernabeu
 

The pmpaddr CSRs have WIRI bits at the top, suggesting to discard bits [63:56].

And when discarding bits, one should assume some value for the discarded bits... but there is however no mention of what value to assume for the discarded bits.

A note explicitly instructing to assume zero would seem like a sensible thing to have.

Regards.


On Thu, Jan 12, 2023 at 12:47 PM <kenney@...> wrote:
Does the RISC-V architecture require particular behavior when physical addresses outside the implemented range are used?

Suppose for example that 56 bits of physical memory are implemented. Is an access with non-zero bits in the range [63:56] required to trap, or is it permitted to discard these bits prior to any PMP checks, effectively wrapping the address range?

(I'm thinking about a system with M+U modes only here.)

Thanks,

James.

Abel Bernabeu
 

With that clarification in place, the comparison of an incoming address against a range happens in the 64 bits space.

On Thu, Jan 12, 2023 at 1:39 PM Abel Bernabeu via lists.riscv.org <abel.bernabeu=esperantotech.com@...> wrote:

The pmpaddr CSRs have WIRI bits at the top, suggesting to discard bits [63:56].

And when discarding bits, one should assume some value for the discarded bits... but there is however no mention of what value to assume for the discarded bits.

A note explicitly instructing to assume zero would seem like a sensible thing to have.

Regards.

On Thu, Jan 12, 2023 at 12:47 PM <kenney@...> wrote:
Does the RISC-V architecture require particular behavior when physical addresses outside the implemented range are used?

Suppose for example that 56 bits of physical memory are implemented. Is an access with non-zero bits in the range [63:56] required to trap, or is it permitted to discard these bits prior to any PMP checks, effectively wrapping the address range?

(I'm thinking about a system with M+U modes only here.)

Thanks,

James.

Paul Donahue
 

In this example, an address above 2^56 would access a vacant PMA region.  Regardless of the outcome of the PMP check, accessing a vacant PMA region will cause an access fault.

I think that you have a very old spec because the upper bits of pmpaddr changed from WIRI to WARL back in version 1.11 and the only legal value is 0.  The whole concept of WIRI hasn't existed for years.
https://github.com/riscv/riscv-isa-manual/commit/92488700503a42b5077a668506a1c6452cb62791


Thanks,

-Paul


On Thu, Jan 12, 2023 at 4:45 AM Abel Bernabeu via lists.riscv.org <abel.bernabeu=esperantotech.com@...> wrote:

With that clarification in place, the comparison of an incoming address against a range happens in the 64 bits space.

On Thu, Jan 12, 2023 at 1:39 PM Abel Bernabeu via lists.riscv.org <abel.bernabeu=esperantotech.com@...> wrote:
The pmpaddr CSRs have WIRI bits at the top, suggesting to discard bits [63:56].

And when discarding bits, one should assume some value for the discarded bits... but there is however no mention of what value to assume for the discarded bits.

A note explicitly instructing to assume zero would seem like a sensible thing to have.

Regards.

On Thu, Jan 12, 2023 at 12:47 PM <kenney@...> wrote:
Does the RISC-V architecture require particular behavior when physical addresses outside the implemented range are used?

Suppose for example that 56 bits of physical memory are implemented. Is an access with non-zero bits in the range [63:56] required to trap, or is it permitted to discard these bits prior to any PMP checks, effectively wrapping the address range?

(I'm thinking about a system with M+U modes only here.)

Thanks,

James.

1 - 4 of 4