Date 1 - 2 of 2
mcycle behavior during stalled wfi
The mcycle CSR is described in the RISC-V Privileged Architecture spec as:
The mcycle CSR counts the number of clock cycles executed by the processor core on which the hart is running.What does 'clock cycles executed by the processor' mean in the context of a WFI instruction? For example, if a core is stalled on a WFI (waiting for e.g. an interrupt to become pending), should mcycle keep incrementing even if for example the remainder of the core's pipeline is clock gated?
mcycle is considered part of the HPM facility.toggle quoted message Show quoted text
If the clock to the core is not running, mcycle does not need to increment.
If part of the core is being clocked (including just mcycle), then mcycle can increment.
Sometimes mcycle counter hardware will also be used to implement mtime, in which case might not want it to stop incrementing during WFI if it’s providing timer interrupt.
The spec allows either interpretation.
The intended use of mcycle is for timing short runs of code with low overhead and high fidelity., and for combining with other HPM values for analysis of code performance.
mtime should be used for wall-clock timing, and might have higher overhead and possibly lower fidelity.
|1 - 2 of 2|