1. Tech-Privileged
  2. Topics

[PATCH] Wait for Interrupt: pause cycle performance counter

andrew@...
 

As alluded to in the unprivileged spec, what you propose is de facto legal because the definition of "cycle" is inherently fuzzy and implementation-dependent.  See this lengthy discussion: https://github.com/riscv/riscv-isa-manual/blob/69c3cd6323381827f3199d0f19ad0cb72ef97155/src/counters.tex#L66-L113

For the same reason, mandating any particular behavior is impractical (and anyway would be a backwards-incompatible change).

On Sat, Feb 12, 2022 at 9:10 PM <guoren@...> wrote:
From: Guo Ren <guoren@...>

Pause cycle performance counter when wfi is implemented with hart
stall. If instruction retire paused then inst cycle also should be
paused, because mcycle & cycle csr is related to instruction retire.

Signed-off-by: Guo Ren <guoren@...>
Cc: Andrew Waterman <andrew@...>
---
 src/machine.tex | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/machine.tex b/src/machine.tex
index 0e4ae9d..66048a4 100644
--- a/src/machine.tex
+++ b/src/machine.tex
@@ -2732,7 +2732,8 @@ WFI  & 0 & PRIV & 0 & SYSTEM \\
 \end{center}

 If an enabled interrupt is present or later becomes present while the
-hart is stalled, the interrupt trap will be taken on the
+hart is stalled, pause cycle performance counter to prevent
+interference IPC statistics, the interrupt trap will be taken on the
 following instruction, i.e., execution resumes in the trap handler and
 {\tt mepc} = {\tt pc} + 4.

--
2.25.1

1 - 1 of 1