1. Tech-Privileged
  2. Topics

platform specific interrupt control

Sanjay Patel <spatel@...>
 

Hi,

The definition of the interrupt pending and enable registers, example mip and mie, define bits 16 and above as available for platform or custom use.

Section 3.1.9 Machine Interrupt Registers (mip and mie) 

Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are available for platform or custom use.

The delegation registers have no similar explicit definition unless I missed it. I will assume that bits 16 and above of mideleg for example are similarly available for platform or custom use.
To be otherwise wouldn't make sense because there is a bit to bit corresponding between all 3 registers. Can these bits be safely implemented in the manner described?

Sanjay
andrew@...
 

Yes, the behavior you'd like follows implicitly from the definition of mideleg.


On Tue, Sep 15, 2020 at 9:23 PM Sanjay Patel <spatel@...> wrote:
Hi,

The definition of the interrupt pending and enable registers, example mip and mie, define bits 16 and above as available for platform or custom use.

Section 3.1.9 Machine Interrupt Registers (mip and mie) 

Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are available for platform or custom use.

The delegation registers have no similar explicit definition unless I missed it. I will assume that bits 16 and above of mideleg for example are similarly available for platform or custom use.
To be otherwise wouldn't make sense because there is a bit to bit corresponding between all 3 registers. Can these bits be safely implemented in the manner described?

Sanjay

1 - 2 of 2