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Svinval fence instructions traps from VU mode

John Ingalls
 

What should the behavior of the SFENCE.W.INVAL and SFENCE.INVAL.IR instructions be when executed in VU mode?  The spec clearly spells out the behavior of the other S/H Fence/Inval instructions in VU mode, and omits these from that list.

I see three options:
  1. Execute without trapping.  I'd vote for this option, and suggest adding this text:
    "Executing SFENCE.W.INVAL or SFENCE.INVAL.IR in VU-mode does not raise an exception if they are allowed in VS-mode."

  2. Illegal instruction exception, just like U-mode.

  3. Virtual instruction exception.  This option is not explicitly prohibited in the spec, but is discouraged by this note:
    "SFENCE.W.INVAL and SFENCE.INVAL.IR instructions do not need to be trapped when mstatus.TVM=1 or when hstatus.VTVM=1, as they only have ordering effects but no vis ible side effects. Trapping of the SINVAL.VMA instruction is sufficient to enable emulation of the intended overall TLB maintenance functionality."

Thanks,
-- John

(Asking the Privileged mailing list since the tech-virt-mem group is archived.)
Andrew Waterman
 

Upon re-reading the relevant section in the hypervisor spec, I believe it is already specified that these should raise virtual-instruction exceptions when executed in VU-mode, hinging on the notion that these are "supervisor instructions": https://github.com/riscv/riscv-isa-manual/blob/5234c630d9eaa13e9654c3a91ef916319950f012/src/hypervisor.tex#L2948-L2950

(And, as you wrote, they should raise illegal-instruction exceptions in U-mode for the same reason: that they are supervisor instructions.)

On Sun, Dec 4, 2022 at 4:53 PM John Ingalls <john.ingalls@...> wrote:
What should the behavior of the SFENCE.W.INVAL and SFENCE.INVAL.IR instructions be when executed in VU mode?  The spec clearly spells out the behavior of the other S/H Fence/Inval instructions in VU mode, and omits these from that list.

I see three options:
  1. Execute without trapping.  I'd vote for this option, and suggest adding this text:
    "Executing SFENCE.W.INVAL or SFENCE.INVAL.IR in VU-mode does not raise an exception if they are allowed in VS-mode."

  2. Illegal instruction exception, just like U-mode.

  3. Virtual instruction exception.  This option is not explicitly prohibited in the spec, but is discouraged by this note:
    "SFENCE.W.INVAL and SFENCE.INVAL.IR instructions do not need to be trapped when mstatus.TVM=1 or when hstatus.VTVM=1, as they only have ordering effects but no vis ible side effects. Trapping of the SINVAL.VMA instruction is sufficient to enable emulation of the intended overall TLB maintenance functionality."

Thanks,
-- John

(Asking the Privileged mailing list since the tech-virt-mem group is archived.)
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