Hi privileged group,

The TEE group are proposing the sPMP mechanism for S-mode physical memory protection. (As linked below)

The TEE group discusses the proposal for quite a while, and we believe that to handle faults generated by sPMP graciously, add three new exception codes for sPMP seems to be reasonable.

sPMP follows the strategy that uses different exception codes for different cases. Currently, sPMP will generate load/store/instruction sPMP faults for memory load, memory store and instruction fetch, respectively.

Since we want to delegate sPMP fault to S-mode rather than handle it in M-mode as PMP did, we wonder whether it is possible to use three bits in the medeleg register.

Please refer to section 2.5 of the sPMP proposal.

Link to the sPMP proposal:
https://docs.google.com/document/d/1x7esOSBFfpcbDHaRPpe5NEWmav1_8der_nB25Hd5hqs/edit#heading=h.rdbq3ygwk878

Best, 
Bicheng