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U bit in G-stage Translation Clarification
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Siqi Zhao
The Privileged Spec says:
Section 5.5.1 "For G-stage address translation, all memory accesses (including those made to access data structures for VS-stage address translation) are considered to be user-level accesses, as though executed in U-mode." What is the exact meaning of 'considered'? Does it mean that even if U bit in the G-stage PTEs is not set, the memory accesses are still 'considered' user-level, i.e. the MMU simply ignore the U bit? Or does it mean that the memory accesses are checked against the U bit? Regards, Siqi |
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Greg Favor
On Mon, Dec 6, 2021 at 12:37 AM Siqi Zhao via lists.riscv.org <zhaosiqi.zsq=alibaba-inc.com@...> wrote: "For G-stage address translation, all memory accesses (including those made to access data structures for VS-stage address translation) are considered to be user-level accesses, as though executed in U-mode." Think "are considered, for permission checking purposes, to be user-level accesses ...". Does it mean that even if U bit in the G-stage PTEs is not set, the memory accesses are still 'considered' user-level, i.e. the MMU simply ignore the U bit? Or does it mean that the memory accesses are checked against the U bit? So No and Yes respectively. In particular, if G-stage U=0, then all these accesses that are treated "as though executed in U-mode", will result in a guest page fault. Greg |
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