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Unsupported counters in 'mcounteren'
Greg Favor
What is the architectural intention for a bit in 'mcounteren' that corresponds to an unsupported hpmcounter (i.e. the hpmcounter register is hardwired to zero)? Can or should this counteren bit also be hardwired to zero, or must it still be writable by software (so as to allow U/S-mode software to read the
hpmcounter
register successfully and get a hardwired zero)?
The definitions for scounteren and hcounteren define these bits as WARL, clearly allowing them to be hardwired to 0. But mcounteren in contrast does not declare these bits to be WARL.
Greg
andrew@...
On Tue, Oct 27, 2020 at 2:53 PM Greg Favor <gfavor@...> wrote:
What is the architectural intention for a bit in 'mcounteren' that corresponds to an unsupported hpmcounter (i.e. the hpmcounter register is hardwired to zero)? Can or should this counteren bit also be hardwired to zero, or must it still be writable by software (so as to allow U/S-mode software to read the hpmcounter register successfully and get a hardwired zero)?The definitions for scounteren and hcounteren define these bits as WARL, clearly allowing them to be hardwired to 0. But mcounteren in contrast does not declare these bits to be WARL.
mcounteren is WARL. An editing error introduced this confusion earlier this year: https://github.com/riscv/riscv-isa-manual/commit/b3d494c7b2ef23dc57225eacd0ac0c165dfa1ddb -- which I'll fix now.
Greg