Hi All, Suppose a hart executes a store to create a new PTE, and then that hart executes a SINVAL.VMA with rs1 and rs2 set so as to affect the address of that PTE. Are subsequent page walks guaranteed

Hi Nick, yes on both - we will plan to end by mid-afternoon on Thursday. Also keeping a zoom call on the 2nd and 3rd day morning (pacific) sounds like a good idea to summarize the previous day and con

Thanks Ravi, I think morning (Pacific time) zoom update calls (one hour?) on the Wednesday and Thursday is probably more social for most people? Than the proposed end of day call (Pacific time). Can w

Started discussion and review of the Sscdeleg and Zicntrpmf fast track extensions, including discussion about how their CSRs are to be used and accessed software. Prior ARC minutes (from two meetings

Started discussion and review of the Sscdeleg and Zicntrpmf fast track extensions, including discussion about how their CSRs are to be used and accessed software. Prior ARC minutes (from two meetings

Hi, Following up from the discussion at the Security HC this week - we discussed the pros of conducting a f2f for the mem isolation topic and there was general consensus to go ahead with it. The days

We discussed a proposal for compressed variants of a subset of the CFI instructions and recommend pursuing it. (This proposal hasn't been written down yet; we will do so soon and will promptly circula

Given that we are all architects, how about we first agree on the problem we are trying solve before debating potential solutions? Ravi, what problem(s) are you trying to solve? I'm guessing its somet

Hello Ravi, It won't be easy for many of us to come to such an event that's focused solely on security and is not a public RISC-V event, or let's say an event large enough that our companies/organizat

Hi Priv TG, In various TGs under the Security HC, and in discussions with folks from this Priv TG, we have been discussing the concept of a dynamic PMA for physical memory isolation (page granular). T

Thanks Ravi, Is this on the agenda for the TC SIG or Security HC this week? Agree it makes sense with focussed meetings on these topics – isolation model, device management model, interoperability wit

Greetings, As active participants in the Security HC know, recently we have been discussing the security model for RISC-V with a focus on (domain) isolation framework. A lot of us have been meeting in

Overview Most of the 2023-02-28 Architecture Review Committee (ARC) discussion concerned the Pointer Masking proposal. This was followed by a brief update on Zimops for CFI, and generalizing the AIA i

To whom it may concern, In RISC-V privileged spec says that mtval2/htval can be written zero when guest page faults occur. I have some questions regarding the statement: 1. Under what circumstance can

Colleagues, James Stine, Ross Thompson, Sarah Harris, and I are writing a textbook on RISC-V System-on-Chip Design, to be published by Elsevier in 2024. It is written around an open-source configurabl

Dong, thank you! this is great. let's make sure as the TG get started that all proposals and POCs get a chance to present their ideas. Also note as a reminder that a number of previous TGs have had wo

Hi all, The ARC recently approved the Instret & Cycle Privilege Mode Filtering (Zicntrpmf) ISA extension to be pursued as a fast-track extension. This extension allows the instret and cycle counters t

Zicond (fast-track): The last PR - to move the DVI text from non-normative to normative text (plus any other last edits) - is to be created shortly by the ARC. After which Zicond should be ready to be

WFMI instruction - The ARC discussed whether the current draft proposal for a WFMI instruction (Wait For "My" Interrupt) had any significant issues for virtualization. The committee concluded it belie

Hi all, Consider the following code sequence, assuming that mcountinhibit.IR has initial value 1: csrc mcountinhibit, 0x4 # uninhibit instret csrs mcountinhibit, 0x4 # inhibit instret My read of the Z