Hello, I am curious why the PMP treats S and U mode accesses identically? Is anyone aware of a standard extension that allows for different permissions for S and U? Thanks, Jeff

Hi, We're submitting for your consideration an extension for resumable non-maskable interrupt (RNMI) support. You might recall that the current non-maskable interrupt support defined in the M-mode cha

Hi all, Here is the third version of the proposal. V2: https://lists.riscv.org/g/tech-privileged/message/1079 V1: https://lists.riscv.org/g/tech-privileged/message/1051 This posting to this email list

When a breakpoint, access-fault, or page-fault exception occur on a CMO instruction (cbo.clean, cbo.flush, cbo.inval, cbo.zero), is the full virtual address provided in the register identified by rs1

The purpose of this e-mail is to start a discussion/debate around the issue that I raised in the tech-chairs meeting this week related the m-mode and the stability of the configuration. It is importan

Greetings ! We are submitting for your consideration an extension for HW PTE A/D updating (Svadu) controls. As you might recall the privileged specification defines two HW behaviors for PTE A/D bits i

We (the AR Committee) will be posting minutes of our (roughly) weekly meetings to discuss ISA issues that have been raised recently to the committee's attention, and to review RV arch extensions that

To whom it may concern, I have a question about guest external interrupt. The privileged ISA said: "GEILEN may be zero". If GEILEN is zero, is the implementation unable to receive guest external inter

To whom it may concern, I have a question about CSR hedeleg and hideleg. The ISA Manual said: "The hedeleg and hideleg CSRs allow these traps to be further delegated to a VS-mode guest." I would like

Dear architect, I don't know the difference between illegal instruction exception and virtual instruction exception. For example: The CSR number of sstatus is 0x100,The CSR number of vsstatus is 0x200

Dear architect, The privileged ISA said: “Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits for supervisorlevel timer interrupts. If implemented, STIP is read-only in sip,

The Sstc specification has this text (referring to whether STIP is writable): If the stimecmp register is *not implemented* , STIP is writable in mip, and may be written by M-mode software to deliver

Dear architect, The stimecmp / vstimecmp” Extension said: "When STCE in menvcfg is zero, an attempt to access stimecmp or vstimecmp in a mode other than M-mode raises an illegal instruction exception,

We (the AR Committee) will be posting minutes of our (roughly) weekly meetings to discuss ISA issues that have been raised recently to the committee's attention, and to review RISC-V arch extensions t

We (the AR Committee) will be posting minutes of our (roughly) weekly meetings to discuss ISA issues that have been raised recently to the committee's attention, and to review RISC-V arch extensions t

Dear architect, CSR mip and vsip are both WARL. But SPEC did not specify that : 1. Are the fields VSEIP，VSSIP，VSTIP in mip real-only ? Can M-mode software modify these bit fields? 2. Are the fields SE

Dear architect, Priv spec section 3.1.6.1 write: “When a hart is executing in privilege mode x, interrupts are globally enabled when xIE=1 and globally disabled when xIE=0. Interrupts for lower-privil

Dear architect, The spec section 3.3.2 said: “An xRET instruction can be executed in privilege mode x or higher, where executing a lower-privilege xRET instruction will pop the relevant lower-privileg

We (the AR Committee) will be posting minutes of our (roughly) weekly meetings to discuss ISA issues that have been raised recently to the committee's attention, and to review RISC-V arch extensions t

What should the behavior of the SFENCE.W.INVAL and SFENCE.INVAL.IR instructions be when executed in VU mode? The spec clearly spells out the behavior of the other S/H Fence/Inval instructions in VU mo