Hi all, This proposal is a refinement and update of a previous thread: https://lists.riscv.org/g/tech-privileged-archive/message/488. We noticed the current activities regarding HPM in Linux community

Hello, Background: You may be aware that the RISC-V Debug Specification 0.13 defines two CSRs, mcontext and scontext, that can be used to qualify hardware breakpoints in a particular OS process or thr

Hi Everyone, This is an updated version of our previous proposal on the clock source and clock event source. We have aligned our ideas with the latest hypervisor extension specs, removed the redundant

Hi, The definition of the interrupt pending and enable registers, example mip and mie, define bits 16 and above as available for platform or custom use. Section 3.1.9 Machine Interrupt Registers (mip

In a belated followup to https://github.com/riscv/riscv-isa-manual/issues/332#issuecomment-466581845, I have the same question as John Hauser. One thing that has changed is that now the architecture h

Hi all, When we applied user-level interrupts in N extension to the Unix-like OS, there is no way to directly handle user-level interrupts in userspace bypassing the kernel. This makes little use of t

I think that there are a few problems in section 5.5.1 of the hypervisor spec. It says that G-stage translation follows the same algorithm as section 4.3.2 with a few changes. However: 1. the first bu

Hi everyone, Can we allocate more CSRs so that we can have more PMP entries available? We already have one implementation which requires 20 PMP entries, for example. Currently the CSR address space ca

HLVX requires execute permission "during address translation" and explicitly requires PMP read access. Since PMP is not address translation, does HLVX require PMP execute permission in addition to rea

Hi all, Andy and I would like to propose the following charter for the CMO TG for approval: The Cache Maintenance Operation, or CMO, task group intends to define data cache maintenance operations for

+1

What is the architectural intention for a bit in 'mcounteren' that corresponds to an unsupported hpmcounter (i.e. the hpmcounter register is hardwired to zero)? Can or should this counteren bit also b

This is just a quick FYI. (Sorry if this is a bit spam'y; there isn't a clear TG to target with this email. And I don't expect that this is something that plays into any near-term RISC-V standardizati

Hi all, quoting the arm manual, "sometimes the OS does need to access unprivileged regions, for example, to write to a buffer owned by an application. To support this, the instruction set provides the

From the Privileged spec, the 2nd step of virtual Address Translation process said, [2. Let pte be the value of the PTE at address a+va.vpn[i]×PTESIZE. (For Sv32, PTESIZE=4.) If accessing pte violates

i found this after some time. this is an extensive set of benchmarks. comparing KASLR enabled and not enabled draw your own conclusions perhaps the summary tells it all https://www.phoronix.com/scan.p

the current size of the virtual address space is 48 bits. (per the june 2019 spec - volume II) as many of you know, INTEL has increased their address space to 57 bits. several designers of server and

Hi, I have some questions about the hpm CSRs. There is a conspicuous lack of an interrupt associated with a counter overflow. Are custom interrupts expected to be provided in a RISC-V implementation?

(+platforms, which Mark had added in.) Thanks for the quick reply Greg. Good to know it is of concern to others. 😊 I assume the specification will be posted for public review in the privileged workgro

Hi TEE group, I would like to give a quick update on ePMP spec. Public review We are still waiting for unpriv group to approve new CSR address assignment. It’s been pending for a while because there’r