+tech-privileged The virt-mem list is quiescent and will go away shortly. Please send questions like this to the governing committee (priv). I have plus'ed them in. Mark

+tech-privileged

Hi, Here is the second version of the proposal. The current Privileged specification only defines Svpbmt for RV64 with the 62-61 bits in PTE, and there are no spare highest bits in rv32 for 34-bit phy

Greetings ! I am sharing a link to a proposal for a Quality of Service (QoS) Identifiers extension. This proposal has been approved by the AR committee to be pursued through the fast-tack extension pr

Hello, I appreciate no guarantees are possible but is it anticipated that the final v1.12 of the RISC-V privileged specification will be the v. 20211203 currently listed on the RISC-V website (https:/

The current Privileged specification only defines Svnapot and Svpbmt for RV64 with the highest bits in PTE, and there are no spare highest bits in rv32 for 34-bit physical addressing. But "the lack of

To add on to Alan's point. These "extension" names were created simply to represent individual line items in the Profiles. In many cases these represent a one or two sentence statement in a Profile ab

Duplicating the information (i.e. having the individual extensions marked and the profile itself indicated) seems like an error-prone proposal, unless we mandate/enforce consistency checking. Given th

If you're looking at the same thing I was looking at: the "extension names" are not extensions, in the usual sense. They are names for the values of architectural options of extensions that already ex

I'm also unclear of the "identifier" you mention for other unmentioned option value (e.g. your 64b cache block size example). Who is the consumer of that identifier? Is this a value you would expect t

Hi All, First off, please redirect me where the most appropriate forum is to discuss this topic. I am casting a fairly wide net, but that's just trying to cover those who are impacted. We can convene

Make rv32 support svpbmt & napot by reducing the PPN witdth (sv32p34 -> sv32p31). RISC-V 32bit also requires svpbmt in cost-down chip embedded scenarios, and their RAM is limited (No more than 1GB). I

This is a call for chair and vice-chair candidates for the recently created Performance Analysis SIG (umbrella: Privileged Software HC) All candidates must submit a biography (bio) and statements of i

Current RISC-V specs only have a non-resumable NMI definition. The following proposal would add resumable NMI support. This was one of the features requested for priv 1.12 or RVA/RVM22. This is up for

Hi, We have a question on github about the implementation of smstateen for Zcmt (table jump). There's the JVT CSR which needs a state enable. The question is whether there is also a state-enable for t

The seed CSR must be accessed with a read-write instruction. A read-only instruction raises an illegal instruction exception. So one could consider the wiping as occurring due to the write and not as

Hi, Maybe the little issue has been solved. I am just curious. The follows come from "4.1. The seed CSR" in Cryptography Extensions Volume I. It talks about the side effect on read the seed CSR. === 4

Hello All, Is there any accessible Linux KVM Nested Virtualization implementation? It doesn't seem like now any open source nested virtualizaion for kvm. Is H-extension now ready for nested virtualiza

As alluded to in the unprivileged spec, what you propose is de facto legal because the definition of "cycle" is inherently fuzzy and implementation-dependent. See this lengthy discussion: https://gith

When only M-mode is implemented, should M-mode be able to access mhpmcounter* via the hpmcounter* CSR number? The spec appears to be unclear. On one hand, it says that all counters should be implement