As alluded to in the unprivileged spec, what you propose is de facto legal because the definition of "cycle" is inherently fuzzy and implementation-dependent. See this lengthy discussion: https://gith

When only M-mode is implemented, should M-mode be able to access mhpmcounter* via the hpmcounter* CSR number? The spec appears to be unclear. On one hand, it says that all counters should be implement

I read this line in the spec : “The matching PMP entry must match all bytes of an access, or the access fails, irrespective of the L, R, W, and X bits.” as an architecture statement. Meaning : If you

Hello, I’ve few queries regarding PMP spec for misaligned access. As per the pmp section in privileged spec, there are two lines as follows: “The matching PMP entry must match all bytes of an access,

Happy new year everybody! Is there a gentle introduction to the RISCV privileged architecture? I'm asking because I have an undergraduate who wants to learn about it so he can contribute Sail code, bu

Hi all, We want to add support for ‘bus errors’ in our RISC-V design (e.g. signaled via AXI bresp/rresp signals). I studied a couple of different RISC-V architectures and I do not see a common approac

Greeting all, I would like to start a discussion on supporting QoS capabilities in RISC-V architecture. I hope I am posting on the right list/TG/HC. First, a short background: Quality of Service (QoS)

The Privileged Spec says: Section 5.5.1 "For G-stage address translation, all memory accesses (including those made to access data structures for VS-stage address translation) are considered to be use

Hi all, I'd like to start a discussion on adding an ability to delegate hardware performance monitoring counters to S/HS mode, and further to VS mode. In “Rich OS” server environments, PMU resources a

Hi Privileged ISA group, There's been a longstanding shortcoming in the RISC-V Privileged ISA document that it doesn't precisely explain what may happen when one CSR controls the writability of bits o

This is the crux of the matter. Can the user understand what the out come will be? Does it match what the user wants it to be? Not all of these examples are this situation, but the most difficult to u

Hello all, In case you missed it we have an IOMMU proposal from Rivos: https://docs.google.com/document/d/1ytBZ6eDk1pAeBlZjDvm6_qqJbKQ0fMYKedyx0uoAGB0/edit The link is now on our wiki with the rest: h

Hi there, I'm working on PMU definition at Rivos, and had some questions about the HPM architecture (including Sscofpmf extension). I started just a couple of weeks ago, and while I tried to do my hom

Hello all, We are about to stabilize the Ssmpu proposal, could you please check it out and provide us with some feedback in case we missed something ? The latest version of the proposal is here: https

please read the attached. i look forward to any and all comments

The syntax is fine, but the version number was meant for pre-ratified extensions during development, not for final production use. There is a related issue of how the support is managed upstream. Ther

Hi Krste, Sounds good. Also we are talking with @Philipp about how to keep compatible with vector v0.7.1 on toolchain interface, we suggest that we prefer this method to control it, e.g. -march=rv64gc

Hi all, Recently the TSC established a lightweight "fast track" architecture extension process that small, straightforward, relatively uncontentious arch extension proposals can utilize. Andrew and I

In RISC-V, instruction fetch addresses and load and store effective addresses are XLEN bits wide; however, an implementation can have a smaller physical address size. When a core is in M-mode or Bare

Hi, Does anyone know why the RV22A profile draft (https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc) mandates the following: misa If the H extension is supported then th