Hi, Could I check my interpretation of the specification with regards to implementing cycle/instret/hpmcountern? It's permissible for an implementation to make these non-accessible in U mode (hard-wir

AR Minutes 1/17/2023 Topics covered in the AR meeting: - Fast interrupts: It was noted that one of the CLIC CSRs had been changed to be read-only, but that the new address was poorly chosen given othe

Pointer-masking extension - On Monday, members of the ARC met with the J Extension Task Group to review the status of the proposed pointer-masking extension. - It is the sense of the ARC that the curr

Hi there, For an implementation that does not support all 29 programmable HPM counters, what is the expected behavior of bits in mcountinhibit and xcounteren associated with the unsupported counters?

Does the RISC-V architecture require particular behavior when physical addresses outside the implemented range are used? Suppose for example that 56 bits of physical memory are implemented. Is an acce

Cache maintenance operations roadmap suggests there are plans to add Cache Block Operations by Index. Has there been any decision if these will be added to the spec? If so, what will be the instructio

Pointer-masking extension - The ARC proposed a meeting with the J Extension Task Group to discuss some specifics of the latest draft proposal. IOMMU - Discussed the ongoing rework of the IOMMU draft s

Procedural - AR plans to write a spec-writing guide in early 2023. - No AR meeting next week. PLIC - Discussed PLIC public review feedback. Removing references to H mode is correct. Furthermore, refer

-------- Abstract -------- Atomic Forward Guarantee is required in many OS to touch contended variables. Linux queued-spinlock is the atomic forward guarantee user who solves the fairness and cache-li

Oscar Jupp wrote: The caption on Table 7.1 says: The effects of hideleg and hvien on vsip and vsie for major interrupts 13-63. Bits 10, 6, and 2 in vsip are major interrupts 10, 6, and 2 for VS level,

This proposal is not appropriate for the fast track, on the basis that it’s far from uncontroversial. It should be discussed at length first.

The priv spec says that a leaf PTE can be at any level of the walk. If you get to step 5 in the "Virtual Address Translation Process" then you've found a leaf PTE. However, if pte.v=0 then you termina

Dear architect， Can the M interrupt such as MTI be delegated to S mode ? Regards, Oscar Jupp

What should the behavior of the SFENCE.W.INVAL and SFENCE.INVAL.IR instructions be when executed in VU mode? The spec clearly spells out the behavior of the other S/H Fence/Inval instructions in VU mo

We (the AR Committee) will be posting minutes of our (roughly) weekly meetings to discuss ISA issues that have been raised recently to the committee's attention, and to review RISC-V arch extensions t

Dear architect, The spec section 3.3.2 said: “An xRET instruction can be executed in privilege mode x or higher, where executing a lower-privilege xRET instruction will pop the relevant lower-privileg

Dear architect, Priv spec section 3.1.6.1 write: “When a hart is executing in privilege mode x, interrupts are globally enabled when xIE=1 and globally disabled when xIE=0. Interrupts for lower-privil

Dear architect, CSR mip and vsip are both WARL. But SPEC did not specify that : 1. Are the fields VSEIP，VSSIP，VSTIP in mip real-only ? Can M-mode software modify these bit fields? 2. Are the fields SE

We (the AR Committee) will be posting minutes of our (roughly) weekly meetings to discuss ISA issues that have been raised recently to the committee's attention, and to review RISC-V arch extensions t

We (the AR Committee) will be posting minutes of our (roughly) weekly meetings to discuss ISA issues that have been raised recently to the committee's attention, and to review RISC-V arch extensions t