Hi Privileged ISA group, There's been a longstanding shortcoming in the RISC-V Privileged ISA document that it doesn't precisely explain what may happen when one CSR controls the writability of bits o

This is the crux of the matter. Can the user understand what the out come will be? Does it match what the user wants it to be? Not all of these examples are this situation, but the most difficult to u

Hello all, In case you missed it we have an IOMMU proposal from Rivos: https://docs.google.com/document/d/1ytBZ6eDk1pAeBlZjDvm6_qqJbKQ0fMYKedyx0uoAGB0/edit The link is now on our wiki with the rest: h

Hi there, I'm working on PMU definition at Rivos, and had some questions about the HPM architecture (including Sscofpmf extension). I started just a couple of weeks ago, and while I tried to do my hom

Hello all, We are about to stabilize the Ssmpu proposal, could you please check it out and provide us with some feedback in case we missed something ? The latest version of the proposal is here: https

please read the attached. i look forward to any and all comments

The syntax is fine, but the version number was meant for pre-ratified extensions during development, not for final production use. There is a related issue of how the support is managed upstream. Ther

Hi Krste, Sounds good. Also we are talking with @Philipp about how to keep compatible with vector v0.7.1 on toolchain interface, we suggest that we prefer this method to control it, e.g. -march=rv64gc

Hi all, Recently the TSC established a lightweight "fast track" architecture extension process that small, straightforward, relatively uncontentious arch extension proposals can utilize. Andrew and I

In RISC-V, instruction fetch addresses and load and store effective addresses are XLEN bits wide; however, an implementation can have a smaller physical address size. When a core is in M-mode or Bare

Hi, Does anyone know why the RV22A profile draft (https://github.com/riscv/riscv-platform-specs/blob/main/riscv-platform-spec.adoc) mandates the following: misa If the H extension is supported then th

scounteren's effect on VU-mode is unclear. VU-mode accesses to HPMn do not necessarily have "insufficient privilege" since hpmcountern is listed in table 2.2 as requiring user privilege. Is scounteren

Hi : I am Kito Cheng, one of the RISC-V open source toolchain developer. Recently RISC-V LLVM and RISC-V GNU toolchain community are discussing how to version control the privilege spec stuff - which

let's create a top sheet and add this please. philipp is working on a review proposal. likely more like tech-announce for 2 weeks and notify TSC and the board. etc Get BlueMail for Android

Hi All, The KVM RISC-V AIA support has been successfully validated with AIA IMSIC virtualization features emulated by QEMU RISC-V. This means KVM RISC-V Guest Linux works perfectly fine with Guest VCP

In a system using SV-39, RISC-V privileged spec defines the behavior of address calculation and page fault detection: Instruction fetch addresses and load and store effective addresses, which are 64 b

Table 3.7 of the privileged spec lists the synchronous exception priorities. The hypervisor chapter adds guest page faults and virtual instruction exceptions but I don't see where it states how they a

Following on to https://github.com/riscv/riscv-isa-manual/pull/701. There should be more said that there's no expectation of implementations "edge detecting" the "becomes pending" event. For example,

mepc, as an example, has this: """ mepc is a WARL register that must be able to hold all valid virtual addresses. It need not be capable of holding all possible invalid addresses. Implementations may

Extrapolating from the discussion on Smepmp discovery, it is reaonable to expect that in the future any security feature will potentially run into the same issue, that is, any data structure is not tr