I reused a topic title under https://github.com/riscv/riscv-isa-manual/issues/131 And also I attached some comments in section 4.4.1 of privileged spec those confused me so much, A. Sv39 implementatio

Hello The Privileged spec says that "ECALL and EBREAK cause the receiving privilege mode’s epc register to be set to the address of the ECALL or EBREAK instruction itself, not the address of the follo

Hi all, The FENCE instruction exposes the difference between accesses to main memory and accesses to I/O devices via the predecessor and successor sets; however, the distinction is really only defined

Hi, We are glad to announce that we are able to boot Linux in KVM guest on a FPGA (Rocket chip + H extension v0.6.1). We now have three hypervisors working on a Hardware with H extension. 1. KVM [1] 2

Hi all, In this proposal, we extended N extension and applied it to H extension for improving the performance of virtual I/O devices in the virtualization scenario. We proposed a new mechanism to dele

attached is a proposal for the definition of RV57K. RV57K is an extension to RV57. the main extension is to incorporate two HARDWARE registers. These registers are used to partition user and kernel ad

My concern is that if an RNMI occurs during an exception handler, and the RNMI handler encounters an exception, the exception return point. cause, and prev. priv state is lost - that's fatal. It's als

One case where NMIs are used on x86 for non-fatal conditions is for performance monitoring. If an operating system wants to accurately measure its own performance, then ideally it should be able to sa

1. I think some of the questions and discussion concerning this proposal have arisen because the proposal is a little too terse. It would be helpful to have more about the specific use cases that the

I am assuming here that NMI is an interrupt, not an exception. Both trap, but an mmie-bit only affects interrupts, not exceptions. So, on entry, the handler knows if this was caused by an NMI or by an

Could you go into more detail on how nesting NMIs could work? Shouldn't it only be safe to execute MNRET with rnmie clear, because any NMI that came in between setting mnepc and executing MNRET would

Hello The privileged architecture says that when returning from interrupt with MRET, MPIE is set to 1 (and MPP is set to U). What is the rational behind ? Is it still in the context of supporting nest

Hi TEE group, I would like to give a quick update on ePMP spec. Public review We are still waiting for unpriv group to approve new CSR address assignment. It’s been pending for a while because there’r

(+platforms, which Mark had added in.) Thanks for the quick reply Greg. Good to know it is of concern to others. 😊 I assume the specification will be posted for public review in the privileged workgro

Hi, I have some questions about the hpm CSRs. There is a conspicuous lack of an interrupt associated with a counter overflow. Are custom interrupts expected to be provided in a RISC-V implementation?

the current size of the virtual address space is 48 bits. (per the june 2019 spec - volume II) as many of you know, INTEL has increased their address space to 57 bits. several designers of server and

i found this after some time. this is an extensive set of benchmarks. comparing KASLR enabled and not enabled draw your own conclusions perhaps the summary tells it all https://www.phoronix.com/scan.p

From the Privileged spec, the 2nd step of virtual Address Translation process said, [2. Let pte be the value of the PTE at address a+va.vpn[i]×PTESIZE. (For Sv32, PTESIZE=4.) If accessing pte violates

Hi all, quoting the arm manual, "sometimes the OS does need to access unprivileged regions, for example, to write to a buffer owned by an application. To support this, the instruction set provides the

This is just a quick FYI. (Sorry if this is a bit spam'y; there isn't a clear TG to target with this email. And I don't expect that this is something that plays into any near-term RISC-V standardizati