Dear architect, The stimecmp / vstimecmp” Extension said: "When STCE in menvcfg is zero, an attempt to access stimecmp or vstimecmp in a mode other than M-mode raises an illegal instruction exception,

The Sstc specification has this text (referring to whether STIP is writable): If the stimecmp register is *not implemented* , STIP is writable in mip, and may be written by M-mode software to deliver

Dear architect, The privileged ISA said: “Bits sip.STIP and sie.STIE are the interrupt-pending and interrupt-enable bits for supervisorlevel timer interrupts. If implemented, STIP is read-only in sip,

Dear architect, I don't know the difference between illegal instruction exception and virtual instruction exception. For example: The CSR number of sstatus is 0x100,The CSR number of vsstatus is 0x200

To whom it may concern, I have a question about CSR hedeleg and hideleg. The ISA Manual said: "The hedeleg and hideleg CSRs allow these traps to be further delegated to a VS-mode guest." I would like

To whom it may concern, I have a question about guest external interrupt. The privileged ISA said: "GEILEN may be zero". If GEILEN is zero, is the implementation unable to receive guest external inter

We (the AR Committee) will be posting minutes of our (roughly) weekly meetings to discuss ISA issues that have been raised recently to the committee's attention, and to review RV arch extensions that

Greetings ! We are submitting for your consideration an extension for HW PTE A/D updating (Svadu) controls. As you might recall the privileged specification defines two HW behaviors for PTE A/D bits i

The purpose of this e-mail is to start a discussion/debate around the issue that I raised in the tech-chairs meeting this week related the m-mode and the stability of the configuration. It is importan

When a breakpoint, access-fault, or page-fault exception occur on a CMO instruction (cbo.clean, cbo.flush, cbo.inval, cbo.zero), is the full virtual address provided in the register identified by rs1

Hi all, Here is the third version of the proposal. V2: https://lists.riscv.org/g/tech-privileged/message/1079 V1: https://lists.riscv.org/g/tech-privileged/message/1051 This posting to this email list

Hi, We're submitting for your consideration an extension for resumable non-maskable interrupt (RNMI) support. You might recall that the current non-maskable interrupt support defined in the M-mode cha

Hello, I am curious why the PMP treats S and U mode accesses identically? Is anyone aware of a standard extension that allows for different permissions for S and U? Thanks, Jeff

Hello, There is something unclear to me after reading the PMA section or the Privileged ISA manual (i.e. Section 3.6). Can a virtual paged be mapped to addresses that cross PMA regions? For example, i

+tech-privileged The virt-mem list is quiescent and will go away shortly. Please send questions like this to the governing committee (priv). I have plus'ed them in. Mark

+tech-privileged

Hi, Here is the second version of the proposal. The current Privileged specification only defines Svpbmt for RV64 with the 62-61 bits in PTE, and there are no spare highest bits in rv32 for 34-bit phy

Greetings ! I am sharing a link to a proposal for a Quality of Service (QoS) Identifiers extension. This proposal has been approved by the AR committee to be pursued through the fast-tack extension pr

Hello, I appreciate no guarantees are possible but is it anticipated that the final v1.12 of the RISC-V privileged specification will be the v. 20211203 currently listed on the RISC-V website (https:/

The current Privileged specification only defines Svnapot and Svpbmt for RV64 with the highest bits in PTE, and there are no spare highest bits in rv32 for 34-bit physical addressing. But "the lack of