If you're looking at the same thing I was looking at: the "extension names" are not extensions, in the usual sense. They are names for the values of architectural options of extensions that already ex

I'm also unclear of the "identifier" you mention for other unmentioned option value (e.g. your 64b cache block size example). Who is the consumer of that identifier? Is this a value you would expect t

Hi All, First off, please redirect me where the most appropriate forum is to discuss this topic. I am casting a fairly wide net, but that's just trying to cover those who are impacted. We can convene

Make rv32 support svpbmt & napot by reducing the PPN witdth (sv32p34 -> sv32p31). RISC-V 32bit also requires svpbmt in cost-down chip embedded scenarios, and their RAM is limited (No more than 1GB). I

This is a call for chair and vice-chair candidates for the recently created Performance Analysis SIG (umbrella: Privileged Software HC) All candidates must submit a biography (bio) and statements of i

Current RISC-V specs only have a non-resumable NMI definition. The following proposal would add resumable NMI support. This was one of the features requested for priv 1.12 or RVA/RVM22. This is up for

Hi, We have a question on github about the implementation of smstateen for Zcmt (table jump). There's the JVT CSR which needs a state enable. The question is whether there is also a state-enable for t

The seed CSR must be accessed with a read-write instruction. A read-only instruction raises an illegal instruction exception. So one could consider the wiping as occurring due to the write and not as

Hi, Maybe the little issue has been solved. I am just curious. The follows come from "4.1. The seed CSR" in Cryptography Extensions Volume I. It talks about the side effect on read the seed CSR. === 4

Hello All, Is there any accessible Linux KVM Nested Virtualization implementation? It doesn't seem like now any open source nested virtualizaion for kvm. Is H-extension now ready for nested virtualiza

As alluded to in the unprivileged spec, what you propose is de facto legal because the definition of "cycle" is inherently fuzzy and implementation-dependent. See this lengthy discussion: https://gith

When only M-mode is implemented, should M-mode be able to access mhpmcounter* via the hpmcounter* CSR number? The spec appears to be unclear. On one hand, it says that all counters should be implement

I read this line in the spec : “The matching PMP entry must match all bytes of an access, or the access fails, irrespective of the L, R, W, and X bits.” as an architecture statement. Meaning : If you

Hello, I’ve few queries regarding PMP spec for misaligned access. As per the pmp section in privileged spec, there are two lines as follows: “The matching PMP entry must match all bytes of an access,

Happy new year everybody! Is there a gentle introduction to the RISCV privileged architecture? I'm asking because I have an undergraduate who wants to learn about it so he can contribute Sail code, bu

Hi all, We want to add support for ‘bus errors’ in our RISC-V design (e.g. signaled via AXI bresp/rresp signals). I studied a couple of different RISC-V architectures and I do not see a common approac

Greeting all, I would like to start a discussion on supporting QoS capabilities in RISC-V architecture. I hope I am posting on the right list/TG/HC. First, a short background: Quality of Service (QoS)

The Privileged Spec says: Section 5.5.1 "For G-stage address translation, all memory accesses (including those made to access data structures for VS-stage address translation) are considered to be use

Hi all, I'd like to start a discussion on adding an ability to delegate hardware performance monitoring counters to S/HS mode, and further to VS mode. In “Rich OS” server environments, PMU resources a

Hi Privileged ISA group, There's been a longstanding shortcoming in the RISC-V Privileged ISA document that it doesn't precisely explain what may happen when one CSR controls the writability of bits o