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Re: [RISC-V tech-announce] Inception of the RERI (RAS Error-record Interface) TG

Greg Favor
 

Resending since there may have been a mixup with the riscv.lists.org being down this morning, and with the soc-infra email missing from the recipient list.  But in any case next Monday morning will be the kickoff meeting for the RERI (RAS Error-record Interface) TG (at 8am PDT).  All interested parties are encouraged to attend.  This meeting is on the RVI tech calendar.  If you have any difficulties, let help@... or me know.  Thanks.

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The RISC-V SOC Infrastructure HC and the RAS SIG together sponsor and announce the inception of the RERI (RAS Error-record Interface) TG, with Greg Favor taking on the responsibilities of acting chair for this group.  RVI members may join this and other groups at lists.riscv.org/groups.

The intent is to develop a RISC-V standard for RAS error logging and reporting registers (similar to what other popular architectures have done).  This is expected to be a Non-ISA specification.  Note that other RAS-related task groups are also being spun up by the RAS SIG to address other aspects of the broad topic of RAS.

The initial meetings will be weekly, starting this coming Monday at 8am (Pacific time).  In consultation with Ved (the SoC Infra chair), we looked at all the RVI meetings across the five mornings of the week and considered what would more likely be conflicting for people that may also be interested in RAS.  There is no conflict-free time slot available, but the clear choice with fewer conflicts looked to be this timeslot.  This should appear on the RVI tech calendar in the next day or so.

The first meeting will be a kickoff for the group, including brief intros by the attendees, summary of some basic logistics, and review of the prelim TG Charter.

We look forward to getting this TG started,
Greg


Inception of the RERI (RAS Error-record Interface) TG

Greg Favor
 

The RISC-V SOC Infrastructure HC and the RAS SIG together sponsor and announce the inception of the RERI (RAS Error-record Interface) TG, with Greg Favor taking on the responsibilities of acting chair for this group.  RVI members may join this and other groups at lists.riscv.org/groups.

The intent is to develop a RISC-V standard for RAS error logging and reporting registers (similar to what other popular architectures have done).  This is expected to be a Non-ISA specification.  Note that other RAS-related task groups are also being spun up by the RAS SIG to address other aspects of the broad topic of RAS.

The initial meetings will be weekly, starting this coming Monday at 8am (Pacific time).  In consultation with Ved (the SoC Infra chair), we looked at all the RVI meetings across the five mornings of the week and considered what would more likely be conflicting for people that may also be interested in RAS.  There is no conflict-free time slot available, but the clear choice with fewer conflicts looked to be this timeslot.  This should appear on the RVI tech calendar in the next day or so.

The first meeting will be a kickoff for the group, including brief intros by the attendees, summary of some basic logistics, and review of the prelim TG Charter.

We look forward to getting this TG started,
Greg

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