SV128 Task Group tech-sv128@lists.riscv.org

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CHARTER FOR DEFINITION OF SV128 FOR RISC-V ARCHITECTURE

Using minicomputers as a starting point, logical addresses from the early to late 70’s grew from 16 to 32 bits. The main driver was main memory dram technology increases. In the early 90’s, the logical address space increased to 64 bits. Again, the main driver was the main memory dram technology increases. Today, in addition to increases in main memory technologies, the creation of cluster and node multicomputer systems has resulted in a step function in memory capacities. This coupled with newer contemporary memory reference models such as PGAS and WEB based referencing models, as well as the introduction of non-volatile memory, results is the need to define SEMANTICS for data references. This contrasts with previous logical address expansion that extended the address space (flat addressing).
Consequently SV128, should be capable of BOTH globally, directly referencing memory, independent of the underlying system architecture, as well as incorporating contemporary security models. Additionally, compatibility with existing RV32 and RV64 executable images need to be supported. As part of this effort, where ever possible, formal methods should be utilized. 
The SV128 working group, will define a 128 virtual address space in 6 months.
 

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