Processor Trace Task Group tech-trace@lists.riscv.org

Group Description

The group shall standardize both a hardware interface to the RISCV core and a packet/data format which will enable the development of commercial and open source trace encoders to be supported by any tools vendors. The interfaces are to provide enough information for: Instruction Trace.  The interfaces should be suitable for in-order and out-of-order cores with extensions.  The group will standardize the data format for: Compressed branch trace so that program flow can be reconstructed by debugging tools.   The group’s progress shall be evaluated after one year at which time the charter may be revised if necessary to narrow the scope of effort.

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