On Sat, 2021-05-29 at 22:42 +0800, Abner Chang wrote:
From: Abner Chang <renba.chang@...>
Initial description of PLIC CLINT section of Linux-2022 platform.
On v6 commit,
Remove the changes in Embedded-2022 section.
On v5 commit,
- Remove CLINT from platform spec
- Require ACLINT on Linux2020 platform and have a link to
- Remove Machine mode timer from previous patch because that is in
the scope of ACLINT
- For Embedded-2022 platform, mention Machine mode timer and refer to
ACLINT for the definition of registers
On v4 commit,
- PLIC section with [DEPRECATED] in Linux- 2022 chapter
- CLINT section in Linux- 2022 chapter for M-mode timer. We don't
IPI because AIA already supported it.
- In Embedded-2022 Machine mode timer section, CLINT is not
- Separate section in appendix for the Machine mode timer registers
On v3 commit,
- Address review comments.
On v2 commit,
- CLINT is not deprecated.
- Add a standalone section for Machine Mode Timer in System
Do you think this is a good place for Machine Mode Timer?
@Mayuresh, please check if you are ok with this change, not sure if
overlaps with your text or not (The timer setion). I can remove
if you prefer to put this with your patch.
- In Embedded-2022, refer to Machine Mode Timer in System Peripherals
section and CLINT in Linux-2022 Platform.
@Alistair, is this ok?
On v1 commit,
- Not sure where to put the [DEPRECATED].
- Change the reference of PLIC in section 2.2.2. Interrupt Controller
126.96.36.199 PLIC + CLINT section.
Signed-off-by: Abner Chang <renba.chang@...>
Cc: Alistair Francis <alistair.francis@...>
Cc: Sunil V L <sunilvl@...>
Cc: Mayuresh Chitale <mchitale@...>
riscv-platform-spec.adoc | 25 ++++++++++++++++++++-----
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 160c74a..c0ee75d 100644
@@ -49,9 +49,24 @@ include::profiles.adoc
* Start Address
==== Interrupt Controller
-* PLIC + CLINT
-* Interrupt Assignments
+The Platform Level Interrupt Controller (PLIC) provides facilities
+the non-local interrupts to the external interrupt of a hart context
+with a given privilege mode in a given hart. The number of non-local
+sources supported by PLIC and how does each of them connect to the
+context is PLIC core implementation-specific. +
IIRC, PLIC spec was never reviewed widely. As this group is more active
now, tt would be good to send it as a separate patch so we can do a
detailed review of that as well.
I am just concerned about semantics rather than technical details.
+for the implementation reference of PLIC operation parameters)
We have now official names for the PLATFORM spec. We should refer to
requires the Advanced Core Local Interruptor (ACLINT,
+to provide facilities to route inter-processor interrupt and Machine
+interrupt to each RISC-V processor hart.
+===== Interrupt Assignments
==== System Peripherals
* UART/Serial Console
@@ -289,8 +304,8 @@ Any RISC-V system that uses at least RV32/64G can
meet the Embedded-2022
==== Interrupt Controller
-Embedded systems are recommended to use a spec compliant
-https://github.com/riscv/riscv-plic-spec[PLIC], a spec compliant
+Embedded systems are recommended to use a spec compliant
+a spec compliant
or both a CLIC and and PLIC.