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- Non-coherent I/O
Re: Non-coherent I/O
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If this is an issue with the priv spec please add it to the priv spec github issues.
On Mon, Jun 14, 2021 at 10:44 AM Josh Scheid <jscheid@...
Accesses by one hart to main memory regions are observable not only by other harts but also
by other devices with the capability to initiate requests in the main memory system (e.g., DMA
engines). Coherent main memory regions always have either the RVWMO or RVTSO memory
model. Incoherent main memory regions have an implementation-defined memory model.
The above is the core normative piece discussion coherent initiators.
It's confusing because the "observable" statement in the first sentence is indirectly overridden by the consideration of incoherent main memory.
It may be enough to add additional wording in the platform spec that for platforms that behave differently for NoSnoop=1 inbound TLPs (vs ignoring them and treating them as NoSnoop=0) the region of addresses accessed in that manner should be communicated as having "incoherent" PMA generally in the system.
But it also implies that there's no standard memory model for incoherent memory. Is the use of RVWMO+Zicmobose sufficient, or is more needed to describe a portable memory model in this case?
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