I have already sent questions to Andrew to get the official view as to the intent of this aspect of the Priv spec and what is the proper way or perspective with which to be reading the ISA specs.  That then may result in the need for clarifying text to be added to the spec.  And once it is clear as to the scope and bounds of the ISA specs and what they require and allow, then it is left to profile and platform specs to specify tighter requirements.

Re I/O-related coherence and ordering, Daniel Lustig will readily acknowledge (and I'm quoting him) that "the I/O ordering model isn't currently defined as precisely as RVWMO".

And Krste will certainly say (i.e. has said) that RISC-V supports systems with coherent and non-coherent masters, and needs to standardize arch support for software management in such platforms asap.