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- Non-coherent I/O
Re: Non-coherent I/O
On Mon, Jun 14, 2021 at 1:04 PM Greg Favor <gfavor@...
I have already sent questions to Andrew to get the official view as to the intent of this aspect of the Priv spec and what is the proper way or perspective with which to be reading the ISA specs. That then may result in the need for clarifying text to be added to the spec. And once it is clear as to the scope and bounds of the ISA specs and what they require and allow, then it is left to profile and platform specs to specify tighter requirements.
Re I/O-related coherence and ordering, Daniel Lustig will readily acknowledge (and I'm quoting him) that "the I/O ordering model isn't currently defined as precisely as RVWMO".
And Krste will certainly say (i.e. has said) that RISC-V supports systems with coherent and non-coherent masters, and needs to standardize arch support for software management in such platforms asap.
While potentially a fine goal, it seems that to make this happen in a manner that allows Platform-compliant SW to be portable, more needs to be done
beyond the Zicmobase work, at least in terms of "glue" specification to tie it all together. It's also possible that the goal of generally enabling non-coherent
masters in RISC-V is perhaps outside the scope of OS-A Platform work, in that in the short term things can be done to enable it in implementation-specific
HW+SW systems, but allowing for implementation portable SW (across platform-compliant implementations) will take longer.
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