Re: Non-coherent I/O

Greg Favor

On Mon, Jun 14, 2021 at 1:04 PM Greg Favor <gfavor@...> wrote:
I have already sent questions to Andrew to get the official view as to the intent of this aspect of the Priv spec and what is the proper way or perspective with which to be reading the ISA specs.  That then may result in the need for clarifying text to be added to the spec.  And once it is clear as to the scope and bounds of the ISA specs and what they require and allow, then it is left to profile and platform specs to specify tighter requirements.
Here's the results of my Q&A with Andrew: 

- The Priv (and Unpriv) ISA specs are just that.  They are CPU architecture specs and should be read with that limited scope in mind.  They may touch on system-level issues, but they are not trying to constrain the flexibility in how these issues are handled across a wide range of system designs.  (I'll personally add on that RVI now makes an official distinction between ISA (Unpriv and Priv) and Non-ISA (aka system-related) arch specs.  The former apply inside of a hart; the latter apply outside of a hart.)

- Per above, PMAs and the PMA coherency attribute are CPU-specific and only apply to memory accesses by harts.  (One can choose to apply these ideas to accesses by other master agents in a system, but that's not officially a Priv spec matter.)

- The PMA coherency attribute only applies to that hart's accesses.  It is up to software to configure the PMAs in all harts to be the same, or not, as desired.  What is done for non-hart accesses (i.e. by I/O devices) is not specified by the Priv spec.  Hence there are no implications on I/O coherency, one way or another, by the Priv spec.

Naturally many if not most system designs will extend these ideas in some manner across the system and to other masters.  And platform specs may choose to specify and mandate some or all of this.  But that's not the business of the ISA specs.


Join to automatically receive all group messages.