Re: [PATCH 1/1] RAS features for OS-A platform server extension

Greg Favor

On Tue, Jun 22, 2021 at 5:34 PM Kumar Sankaran <ksankaran@...> wrote:
I think the primary requirements here are the following:
- The platform should provide the capability to configure each RAS
error to trigger firmware-first or OS-first error interrupt.

Yes.  Which is just a software matter of configuring the interrupt controller accordingly.
- If the RAS error is handled by firmware, the firmware should be able
to choose to expose the error to S/HS mode for further processes or
just hide the error from S/HS software.
Is there a need to provide all the other details?

Agreed.  The details and mechanics don't need to be discussed (unless they are mandating specific mechanics - which I don't believe is the case). 

> Yes, to mask the RAS error interrupt or even not to create the log (in RAS status registers or CSR) that OEM doesn't consider that is a useful or important error to product.

This is fine

Maybe just say that "Logging and/or reporting of errors can be masked".
Can we summarize the requirement to
- RAS errors should be capable of interrupting TEE.

This implies a requirement to have a TEE - and defining what constitutes a compliant TEE in the platform spec.  Btw, what distinguishes the TEE from "firmware"?
The PCIe AER errors have been handled OS first on X86 systems. If I
recall correct, ARM64 initially made PCIe AER errors firmware first
and then later changed to OS first to be compliant with what's already
out there.
The exact manner of handling these PCIe AER errors is also OEM
dependent. Some OEMs will handle it OS first while making a call to
the firmware to take additional corrective action of notifying the BMC
and such. Some ARM64 implementations handle this firmware first and
notify the BMC and then notify the OS.
From a RISC-V platforms requirements perspective, my suggestion is we
simply mention the capability of all errors to have support for
firmware first and OS first and leave it at that.

Agreed all around.


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