Re: [PATCH 1/1] Cache Coherency and ASID Requirements for OS-A platform

Daniel Lustig

On 6/25/2021 4:04 AM, Kumar Sankaran wrote:
Hi Andrew,

Agree with your comment on the RVWMO memory model requirement. Since this
requirement is for the OS-A platform, providing an additional level of
clarity will help since all implementations will be having a cache
sub-system. So how about the below wording?

- All harts must adhere to the RVWMO memory model. Consequently, any
hart-related caches must all be hardware coherent with respect to each
other, and must appear to software as physically-indexed, physically-tagged
(PIPT) caches.
I agree with Andrew. What does it mean for caches to appear to software
in any particular way? Unless you're talking about something like CMOs,
aren't caches entirely transparent to software?

In any case, what's wrong with VIPT caches?

- Memory accesses by I/O masters can be coherent or non-coherent with
respect to any hart-related caches
Since we're aiming for clarity here, if we do keep this wording (and
I'm not saying we should), can we also clarify whether this implies
anything about the coherence PMAs? IIUC the PMAs represent the harts'
perspective on memory, so those would generally (or possibly always
in the OS-A platform?) mark main memory regions as coherent, even if
external devices may access that same memory non-coherently?




*From:* Andrew Waterman <andrew@...>
*Sent:* Thursday, June 24, 2021 11:24 PM
*To:* Kumar Sankaran <ksankaran@...>
*Cc:* tech-unixplatformspec@...; Daniel Lustig <
*Subject:* Re: [RISC-V] [tech-unixplatformspec] [PATCH 1/1] Cache Coherency
and ASID Requirements for OS-A platform

+ Dan

I'm not sure it makes sense to include the cache coherence requirement--not
because we wish to permit incoherent caches, but because it's a constraint
specified at the wrong level of abstraction. The fundamental requirement
is that the harts adhere to the RVWMO memory model. The concept of caches
and the concept of coherence are implementation details. (Yes, in
practice, if you have caches, you'll need cache coherence to implement
RVWMO, but that doesn't mean it should be in a list of requirements.)

On Thu, Jun 24, 2021 at 7:00 PM Kumar Sankaran <ksankaran@...>

This patch adds the following
Cache coherency and ASID requirements
Interrupt Controller and PMU chapter sub-sections for OS-A base and
Server Extension

diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 87ea6d5..b985f50 100644
--- a/riscv-platform-spec.adoc
+++ b/riscv-platform-spec.adoc
@@ -88,8 +88,12 @@ The M platform has the following extensions:
* ISA Profile
** The OS-A platform is required to comply with the RVA22 profile.
* Cache Coherency
-* PMU
+** All HART related caches must be hardware coherent and must appear to
+software as Physically Indexed, Physically Tagged (PIPT) caches
+** Memory accesses by I/O masters can be coherent or non-coherent with
+to the HART related caches
+==== PMU

==== Debug
The OS-A base platform requirements are -
@@ -287,10 +291,12 @@ base with the additional requirements as below.
==== Architecture
The platforms which conform to server extension are required to implement +

-- RISC-V Hypervisor-level H Instruction-Set Extensions
-- IOMMU with support for memory resident interrupt files
-- PMU
+- RV64 support
+- RISC-V H ISA extension
+- ASID support
+- VMID support
+==== PMU

==== Debug
The OS-A server platform requirements are all of the base above plus:
@@ -305,6 +311,8 @@ above.
respect to all harts connected to the DM
* Rationale: Debuggers must be able to view memory coherently

+==== Interrupt Controller
==== Boot and Runtime Requirements
===== Firmware
The boot and system firmware for the RV64I server platforms required to be

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