Re: [PATCH 1/1] Cache Coherency and ASID Requirements for OS-A platform


Greg Favor
 

On Fri, Jun 25, 2021 at 5:22 AM Philipp Tomsich <ptomsich@...> wrote:
I agree with Andrew.  What does it mean for caches to appear to software
in any particular way?  Unless you're talking about something like CMOs,
aren't caches entirely transparent to software?

The intent seems to be that caches shall appear (to software) to be non-aliasing.

ARM went through this issue with the variety of CPU designs that people have done (both outside and inside ARM).  In particular, as people went to larger and/or more power-efficient L1 caches, they implemented VIPT caches.  Which exposes VA aliasing to software.  So either software has to manage cache consistency, or hardware has to (i.e hardware has to make the VIPT cache appear to behave like a PIPT cache).  That's non-trivial hardware, but not unreasonable.  The result is that while ARM architecture allows VIVT, VIPT, and PIPT caches, in A class cores everything has moved to caches that appear to be PIPT while many actually are VIPT designs.

One can say that RVWMO compliance implies a requirement that caches appear to behave like PIPT caches.  But, given the growing use of VIPT caches, it's worth half a sentence to make clear the implications of RVWMO.
 
 
In any case, what's wrong with VIPT caches?

Depends on the internal organisation of a VIPT cache (and its size/number of index bits)...
The requirement clearly is that the cache appears to be non-aliasing, by whatever design choices.
A simple rewording of the original statement to this effect (instead of referencing PIPT) should address this.

Agreed.  I'll come up with some better words for Kumar to use.
 
 
> - Memory accesses by I/O masters can be coherent or non-coherent with
> respect to any hart-related caches

Since we're aiming for clarity here, if we do keep this wording (and
I'm not saying we should), can we also clarify whether this implies
anything about the coherence PMAs?  IIUC the PMAs represent the harts'
perspective on memory, so those would generally (or possibly always
in the OS-A platform?) mark main memory regions as coherent, even if
external devices may access that same memory non-coherently?

People tend to presume this in OS/A-class systems, but yes this should be explicitly stated.

Greg

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