[PATCH 3/3] Add PMU section
Signed-off-by: Atish Patra <atish.patra@...>
riscv-platform-spec.adoc | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/riscv-platform-spec.adoc b/riscv-platform-spec.adoc
index 5f52edf47a44..c59f4b8d4363 100644
@@ -72,6 +72,9 @@ The M platform has the following extensions:
|APLIC | Advanced PLIC
|AIA | Advanced Interrupt Architecture
|IMSIC | Incomning MSI Controller
+|L1D | L1 Data cache
+|LL | Last level cache
+|DTLB | DATA TLB cache
@@ -103,6 +106,18 @@ to all hart-related caches.
+The RVA22 profile defines 32 PMU counters out-of-which first three counters are
+defined by the privilege specification while other 29 counters are programmable.
+The SBI PMU extension defines a set of hardware events that can be monitored using
+these programmable counters. This section defines the minimum number of programmable
+counters and hardware events required for an OS-A compatible platform.
+** The platform do not require to implement any of the programmable counters.
+** The platform do not require to implement any of the hardware events defined
+in SBI PMU extensions.
The OS-A base platform requirements are -
@@ -409,6 +424,16 @@ The platforms which conform to server extension are required to implement +
+** The platform must implement at least 8 programmable counters.
+** Hardware general events
+*** The platform must implement all of the general hardware events defined by
+the SBI PMU extension.
+** Hardware cache events
+*** The platform must implement all of the hardware cache events for READ operations
+while WRITE operation must be implemented for L1D, LL and DTLB caches.
The OS-A server platform requirements are all of the base above plus: