Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Josh Scheid

> The MTIME register is a 64-bit read-write register

Is the device required to allow only 64-bit accesses to these registers?  Can a device allow 32-bit accesses?  Can a device only support 32-bit accesses?  If only one size or the other, how will SW know (e.g., in DT)?


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