Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub
Both MTIME and MTIMECMP are 64-bit wide registers from device perspective (i.e. from ACLINT specification perspective). The ACLINT specification does not mandate 32-bit or 64-bit accesses for RISC-V HARTs. This means by default software will assume 64-bit accesses on RV64 and 32-bit accesses on RV32. We can certainly have an optional boolean DT property “mtimer,64bit-access-not-supported” which will force software to use 32-bit accesses on RV64 system.
Regards,
Anup
From: Josh Scheid <jscheid@...>
Date: Saturday, 17 July 2021 at 12:02 AM
To: Greg Favor <gfavor@...>
Cc: Anup Patel <Anup.Patel@...>, "tech-aia@..." <tech-aia@...>, "tech-unixplatformspec@..." <tech-unixplatformspec@...>, Atish Patra <Atish.Patra@...>, Alistair Francis <Alistair.Francis@...>,
Andrew Waterman <andrew@...>, John Hauser <jh.riscv@...>
Subject: Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub
Lastly, it seems like all this can just be said in the ACLINT spec. The platform specs will automatically then inherit this as part of using ACLINT (or parts of ACLINT).
The optional 64-bit access option from HW would need to be communicated in discovery/DT.
-Josh