Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub
On Fri, Jul 16, 2021 at 9:31 PM Andrew Waterman <andrew@...> wrote:
Common AMBA utility bus standards like the AXI-Lite buses don't support burst accesses - and hence the bus width does set the access width. These bus standards are intended to be simple and sufficient for accessing memory-mapped registers.
It was provided earlier in this email thread - which I'll forward to you in a minute.