Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Greg Favor

On Fri, Jul 16, 2021 at 9:31 PM Andrew Waterman <andrew@...> wrote:
  Who wants to spend the hardware on a 2x wide bus for negligible benefit.

While I agree, I view this as an almost orthogonal concern: bus width doesn’t set a limit on access width.

Common AMBA utility bus standards like the AXI-Lite buses don't support burst accesses - and hence the bus width does set the access width.  These bus standards are intended to be simple and sufficient for accessing memory-mapped registers.

The point of what was suggested as a result of the email discussions with Andrew a year ago, is that support for the common case should be required (e.g. 32-bit accesses) and then have a DT property that says 64-bit accesses may also be used by software.

I have to admit I don’t recall that thread. Can you forward along a pointer?

It was provided earlier in this email thread - which I'll forward to you in a minute.


Join to automatically receive all group messages.