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Re: [tech-aia] RISC-V ACLINT specification is now hosted on RISC-V GitHub

Greg Favor
 

On Fri, Jul 16, 2021 at 10:19 PM Greg Favor via lists.riscv.org <gfavor=ventanamicro.com@...> wrote:
On Fri, Jul 16, 2021 at 10:10 PM Greg Favor <gfavor@...> wrote:
Common AMBA utility bus standards like the AXI-Lite buses don't support burst accesses - and hence the bus width does set the access width.  These bus standards are intended to be simple and sufficient for accessing memory-mapped registers.

Add to the list the popular APB bus standard used by many IPs for access to their memory-mapped registers.  It only supports up to 32-bit accesses.

In essence, is RV64 going to effectively outlaw ready use of common 32-bit "utility" AMBA bus standards in RV64 systems (especially since there will be a growing number of 64-bit memory-mapped registers defined by extensions this year and going forward)?

Greg


 
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